MFB PD ASFIFO SIMPLE

ENTITY MFB_PD_ASFIFO_SIMPLE IS

Generics

Generic	Type	Default	Description
=====	MFB parameters	=====	=====
MFB_REGIONS	natural	4
MFB_REGION_SIZE	natural	8
MFB_BLOCK_SIZE	natural	8
MFB_ITEM_WIDTH	natural	8
MFB_META_WIDTH	natural	2
=====	FIFO PARAMETERS	=====	=====
FIFO_ITEMS	natural	512	FIFO depth in number of data words, must be power of two!
AFULL_OFFSET	natural	FIFO_ITEMS/2	Sets the maximum number of remaining free data words in the FIFO that triggers the RX_AFULL signal.
DEVICE	string	“AGILEX”	Defines target FPGA device.

Ports

Port	Type	Mode	Description
=====	RX MFB interface	=====	Runs on RX_CLK
RX_CLK	std_logic	in
RX_RESET	std_logic	in
RX_DATA	std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	in
RX_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	in
RX_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)	in
RX_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	in
RX_SRC_RDY	std_logic	in
RX_DST_RDY	std_logic	out
RX_DISCARD	std_logic_vector(MFB_REGIONS-1 downto 0)	in	Discard flag valid with each EOF
RX_AFULL	std_logic	out	Almost full flag
=====	TX MFB interface	=====	Runs on TX_CLK
TX_CLK	std_logic	in
TX_RESET	std_logic	in
TX_DATA	std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	out
TX_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	out
TX_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)	out
TX_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	out
TX_SRC_RDY	std_logic	out
TX_DST_RDY	std_logic	in