Gen Loop Switch (GLS)

ENTITY GEN_LOOP_SWITCH IS

This unit contains MI32-configurable switch plane for connection between DMA Module and Ethernet side in both RX and TX stream. By default the connection is ETH_RX->DMA_RX and DMA_TX->ETH_TX. It allows for loopback between ETH_RX->ETH_TX and DMA_TX->DMA_RX as well as connection of MFB generators on DMA_RX and ETH_TX. These generators have their own part of MI32 address space.

Connection diagram:

                      +--------+  +---\
                      | RX Gen +--+ 1  \             +---\
ETH_RX                +--------+  |MUX_C+------------+ 0  \   +------+ DMA_RX
>--------------------------+------+ 0  /             |MUX_A+--+ FIFO +------>
                           |      +---/          +---+ 1  /   +------+
                           |                     |   +---/
                           |                     |
                           |                     |
                           |                     |
                   /---+   |                     |
       +------+   /  1 +---+          /---+      |
<------+ FIFO +--+MUX_B|             /  0 +------+--------------------------<
ETH_TX +------+   \  0 +------------+MUX_D|  +-----------------+       DMA_TX
                   \---+             \  1 +--+ TX Gen / Player |
                                      \---+  +-----------------+

MI address offsets:

0x000      -- RX loopback MUX_A  (0 -> RX stream, 1 -> TX stream loopback)
0x004      -- TX loopback MUX_B  (0 -> TX stream, 1 -> RX stream loopback)
0x008      -- RX generator MUX_C (0 -> RX stream, 1 -> RX generator)
0x00C      -- TX generator MUX_D (0 -> TX stream, 1 -> TX generator, 2 -> TX Frame Player)
0x040-0x04C -- DMA RX MFB speed meter (0x0 - tics, 0x4 - status, 0x8 - items, 0xC - clear)
0x050-0x05C -- DMA TX MFB speed meter (0x0 - tics, 0x4 - status, 0x8 - items, 0xC - clear)
0x060-0x06C -- ETH RX MFB speed meter (0x0 - tics, 0x4 - status, 0x8 - items, 0xC - clear)
0x070-0x07C -- ETH TX MFB speed meter (0x0 - tics, 0x4 - status, 0x8 - items, 0xC - clear)
0x080-0x0BF -- RX generator address space
0x0C0-0x0FF -- TX generator address space
free address space from 0x100-0x17F
0x180-0x1BF -- RX Frame Player address space
0x1C0-0x1FF -- TX Frame Player address space

Notes:
- Only the lowest 8 bits of address considered.
- Generator address offsets -> see entity of subcomponent MFB_GENERATOR_MI32

Warning

Only switch mux selection registers when there is no data on the input!

Generics

Generic	Type	Default	Description
REGIONS	natural	2	number of regions in a data word
REGION_SIZE	natural	8	number of blocks in a region
BLOCK_SIZE	natural	8	number of items in a block
ITEM_WIDTH	natural	8	number of bits in an item
PKT_MTU	natural	16383	maximum supported packet MTU in bytes
RX_DMA_CHANNELS	natural	32	number of supported DMA channels on RX
NPP_HDR_SIZE	natural	4	size of NPP Header (in bytes) must not be greater than BLOCK_SIZE*ITEM_WIDTH/8
TX_DMA_CHANNELS	natural	32	number of supported DMA channels on TX
HDR_META_WIDTH	natural	12	Width of User Header Metadata information
PLAYER_FIFO_DEPTH	natural	512	Depth of FIFO memory in MFB FRAME PLAYERs
RX_HDR_INS_EN	boolean	false	enable inserting generated NPP Header at the start of each MFB frame in RX generator
SAME_CLK	boolean	false	MI_CLK and CLK are the same set this to True to remove MI asynch conversion
MI_PIPE_EN	boolean	true	MI PIPE enable
FAKE_SWITCH	boolean	false	Setting this to True will disable the component and create direct connection from DMA interfaces to ETH interfaces
DEVICE	string	“STRATIX10”	FPGA device string

Ports

Port	Type	Mode	Description
MI_CLK	std_logic	in
MI_RESET	std_logic	in
MI_DWR	std_logic_vector(32-1 downto 0)	in
MI_ADDR	std_logic_vector(32-1 downto 0)	in
MI_BE	std_logic_vector(32/8-1 downto 0)	in	Not supported!
MI_RD	std_logic	in
MI_WR	std_logic	in
MI_ARDY	std_logic	out
MI_DRD	std_logic_vector(32-1 downto 0)	out
MI_DRDY	std_logic	out
CLK	std_logic	in	Internal clock and reset for all interfaces besides MI32
RESET	std_logic	in
ETH_RX_MVB_LEN	std_logic_vector(REGIONS*log2(PKT_MTU+1)-1 downto 0)	in	MVB interface with DMA instructions
ETH_RX_MVB_CHANNEL	std_logic_vector(REGIONS*log2(RX_DMA_CHANNELS)-1 downto 0)	in
ETH_RX_MVB_HDR_META	std_logic_vector(REGIONS*HDR_META_WIDTH-1 downto 0)	in
ETH_RX_MVB_DISCARD	std_logic_vector(REGIONS*1-1 downto 0)	in
ETH_RX_MVB_VLD	std_logic_vector(REGIONS-1 downto 0)	in
ETH_RX_MVB_SRC_RDY	std_logic	in
ETH_RX_MVB_DST_RDY	std_logic	out
ETH_RX_MFB_DATA	std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)	in	MFB interface with data packets
ETH_RX_MFB_SOF	std_logic_vector(REGIONS-1 downto 0)	in
ETH_RX_MFB_EOF	std_logic_vector(REGIONS-1 downto 0)	in
ETH_RX_MFB_SOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)	in
ETH_RX_MFB_EOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)	in
ETH_RX_MFB_SRC_RDY	std_logic	in
ETH_RX_MFB_DST_RDY	std_logic	out
ETH_TX_MVB_LEN	std_logic_vector(REGIONS*log2(PKT_MTU+1)-1 downto 0)	out	MVB interface with DMA instructions
ETH_TX_MVB_CHANNEL	std_logic_vector(REGIONS*log2(TX_DMA_CHANNELS)-1 downto 0)	out
ETH_TX_MVB_HDR_META	std_logic_vector(REGIONS*HDR_META_WIDTH-1 downto 0)	out
ETH_TX_MVB_VLD	std_logic_vector(REGIONS-1 downto 0)	out
ETH_TX_MVB_SRC_RDY	std_logic	out
ETH_TX_MVB_DST_RDY	std_logic	in
ETH_TX_MFB_DATA	std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)	out	MFB interface with data packets
ETH_TX_MFB_SOF	std_logic_vector(REGIONS-1 downto 0)	out
ETH_TX_MFB_EOF	std_logic_vector(REGIONS-1 downto 0)	out
ETH_TX_MFB_SOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)	out
ETH_TX_MFB_EOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)	out
ETH_TX_MFB_SRC_RDY	std_logic	out
ETH_TX_MFB_DST_RDY	std_logic	in
DMA_RX_MVB_LEN	std_logic_vector(REGIONS*log2(PKT_MTU+1)-1 downto 0)	out	MVB interface with DMA instructions
DMA_RX_MVB_CHANNEL	std_logic_vector(REGIONS*log2(RX_DMA_CHANNELS)-1 downto 0)	out
DMA_RX_MVB_HDR_META	std_logic_vector(REGIONS*HDR_META_WIDTH-1 downto 0)	out
DMA_RX_MVB_DISCARD	std_logic_vector(REGIONS*1-1 downto 0)	out
DMA_RX_MVB_VLD	std_logic_vector(REGIONS-1 downto 0)	out
DMA_RX_MVB_SRC_RDY	std_logic	out
DMA_RX_MVB_DST_RDY	std_logic	in
DMA_RX_MFB_DATA	std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)	out	MFB interface with data packets
DMA_RX_MFB_SOF	std_logic_vector(REGIONS-1 downto 0)	out
DMA_RX_MFB_EOF	std_logic_vector(REGIONS-1 downto 0)	out
DMA_RX_MFB_SOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)	out
DMA_RX_MFB_EOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)	out
DMA_RX_MFB_SRC_RDY	std_logic	out
DMA_RX_MFB_DST_RDY	std_logic	in
DMA_TX_MVB_LEN	std_logic_vector(REGIONS*log2(PKT_MTU+1)-1 downto 0)	in	MVB interface with DMA instructions
DMA_TX_MVB_CHANNEL	std_logic_vector(REGIONS*log2(TX_DMA_CHANNELS)-1 downto 0)	in
DMA_TX_MVB_HDR_META	std_logic_vector(REGIONS*HDR_META_WIDTH-1 downto 0)	in
DMA_TX_MVB_VLD	std_logic_vector(REGIONS-1 downto 0)	in
DMA_TX_MVB_SRC_RDY	std_logic	in
DMA_TX_MVB_DST_RDY	std_logic	out
DMA_TX_MFB_DATA	std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)	in	MFB interface with data packets
DMA_TX_MFB_SOF	std_logic_vector(REGIONS-1 downto 0)	in
DMA_TX_MFB_EOF	std_logic_vector(REGIONS-1 downto 0)	in
DMA_TX_MFB_SOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)	in
DMA_TX_MFB_EOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)	in
DMA_TX_MFB_SRC_RDY	std_logic	in
DMA_TX_MFB_DST_RDY	std_logic	out