Packet Delayer

ENTITY MFB_PACKET_DELAYER IS

Incoming packets with Timestamps [ns] are stored in the RX FIFO. From there each packet is read when the Stored time value reaches the packet’s Timestamp value. There are 2 Timestamp formats that are currently supported (see the TS_FORMAT generic). The packets read from the RX FIFO are stored in the TX FIFO.

Generics

Generic	Type	Default	Description
MFB_REGIONS	natural	1	Number of Regions within a data word, must be power of 2.
MFB_REGION_SIZE	natural	8	Region size (in Blocks).
MFB_BLOCK_SIZE	natural	8	Block size (in Items), must be 8.
MFB_ITEM_WIDTH	natural	8	Item width (in bits), must be 8.
MFB_META_WIDTH	natural	0	Metadata width (in bits).
TS_WIDTH	natural	48	Width of Timestamps (in bits).
TS_FORMAT	natural	0	Format of Timestamps. Options: 0 number of NS between individual packets, 1 number of NS from RESET.
FIFO_DEPTH	natural	2048	Number of Items in the Input MFB_FIFOX (main buffer).
FIFO_AF_OFFSET	natural	1000	Almost Full Offset of the Input MFB_FIFOX. Pauses the appropriate DMA channel when the amount of stored Items reaches this value.
FIFO_AE_OFFSET	natural	1000	Almost Empty Offset of the input MFB_FIFOX. Unpauses (resumes) the appropriate DMA channel when the amount of stored Items drops under this value.
DEVICE	string	“STRATIX10”	FPGA device name: ULTRASCALE, STRATIX10, AGILEX, …

Ports

Port	Type	Mode	Description
=====	Clock and Reset	=====	=====
CLK	std_logic	in
RESET	std_logic	in
TIME_RESET	std_logic	in	Reset time accumulation (applies only when TS_FORMAT=1). Time counter is reset with the next first SOF.
CURRENT_TIME	std_logic_vector(64-1 downto 0)	in	A 64-bit value representing Time, which is used to decide whether a packet’s Timestamp is OK and can be transmitted or not. It can be a precise time from the TSU, a value from a simple incrementing counter, or anything in between. The quality of the time source affects the precision of the packet’s transmission but not the component’s functionality.
PAUSE_REQUEST	std_logic	out	Used to pause incomming traffic when the buffer is Almost Full.
=====	RX inf	=====	=====
RX_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	in
RX_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	in	Valid with SOF.
RX_MFB_TS	std_logic_vector(MFB_REGIONS*TS_WIDTH-1 downto 0)	in	Timestamp valid with each SOF.
RX_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)	in
RX_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	in
RX_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX_MFB_SRC_RDY	std_logic	in
RX_MFB_DST_RDY	std_logic	out
=====	TX inf	=====	=====
TX_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	out
TX_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	out	Valid with SOF.
TX_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)	out
TX_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	out
TX_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_SRC_RDY	std_logic	out
TX_MFB_DST_RDY	std_logic	in

Block diagram