Timestamp Limiter
- ENTITY MFB_TIMESTAMP_LIMITER IS
This component limits output speed according to given Timestamps via the
RX_MFB_TIMESTAMPport. There are 2 Timestamp formats that are currently supported (see theTIMESTAMP_FORMATgeneric). The incoming packets are split into queues (e.g., per each DMA Channel), where the order of packets is kept the same. Then in each Selected Queue, the MFB Packet Delayer component outputs each packet when the time is right. Selected Queues are a subset of all available Queues in range 0 toSELECTED_QUEUES-1. Only in these Selected Queues are the packets transmitted according to the Timestamps; FIFOs are in the other “unselected” Queues. Finally, behind the Packet Delayers and FIFOs, the packets from all Queues are merged back into a single stream (no order is kept here).The Packet Delayers use a time source, according to which they calculate the time that has passed and whether a packet is due to be sent. The default is to use the so-called Time Counter (see diagram below), which is basically a counter that increments its value by the duration of one clock period derived from the value of the
CLK_FREQUENCYgeneric. Another option is to use an external time source, for example, the TSU (for better precision). In this case, set theEXTERNAL_TIME_SRCgeneric toTrueand connect your time source to theEXTERNAL_TIMEport.The MI interface enables the user to do two things.
#. Reset the accumulated “time” in the Packet Delayers. This is useful when using the
Timestamp format 1, where the time is being incremented in each clock cycle since the very first packet after boot/reset passes through. You can simply reset all Packet Delayers (all Queues) by setting the MI_RESET_REG register, or you can select specific Queues by setting the MI_SEL_QUEUE_REG register before setting the MI_RESET_REG register. After writing a 1 to the MI_RESET_REG register to issue the reset, its value automatically returns back to 0. #. Bypass timestamp limiting and transmit data at top speed. When enabled, all timestamp values are automatically set to 0 and all packets are redirected to Queue 0 to avoid merging at the end. NOTE that the top speed is ON in the default state! To enable timestamp limiting, write 0 to the MI_TOP_SPEED_REG register.MI address space
GenericsAddress offset
MI Register
0x00
Reset register (write only)
0x04
Select Queues for reset register
0x08
Top speed register
PortsGeneric
Type
Default
Description
MFB_REGIONS
natural
1
Number of Regions within a data word, must be power of 2.
MFB_REGION_SIZE
natural
8
Region size (in Blocks).
MFB_BLOCK_SIZE
natural
8
Block size (in Items), must be 8.
MFB_ITEM_WIDTH
natural
8
Item width (in bits), must be 8.
MFB_META_WIDTH
natural
0
Metadata width (in bits).
MI_DATA_WIDTH
natural
32
MI_ADDR_WIDTH
natural
32
CLK_FREQUENCY
natural
200000000
Freq of the CLK signal (in Hz).
TIMESTAMP_WIDTH
natural
48
Width of Timestamps (in bits).
TIMESTAMP_FORMAT
natural
0
Format of Timestamps. Options:
0number of NS between individual packets,1number of NS from RESET.
EXTERNAL_TIME_SRC
boolean
False
Select Time source. Options:
True - use external source of time (port
EXTERNAL_TIME), False (default) - internal “Time Counter” with increment given by CLK_FREQUENCY.BUFFER_SIZE
natural
2048
Number of Items in the Packet Delayer’s RX FIFO (the main buffer).
BUFFER_AF_OFFSET
natural
10
Almost Full Offset of the main buffer in Packet Delayers. States the number of data words it can accept after Almost Full is asserted.
QUEUES
natural
1
The number of Queues (DMA Channels).
SELECTED_QUEUES
natural
QUEUES
The number of selected Queues (DMA Channels) for timestamp limiting. The range is from 0 to SELECTED_QUEUES-1. Timestamps in other Queues are ignored as packets pass through FIFOs instead of Packet Delayers.
DEVICE
string
“STRATIX10”
FPGA device name: ULTRASCALE, STRATIX10, AGILEX, …
Port
Type
Mode
Description
=====
Clock and Reset
=====
=====
CLK
std_logic
in
RESET
std_logic
in
EXTERNAL_TIME
std_logic_vector(64-1 downto 0)
in
Connect your own Time source to this port (used when the
EXTERNAL_TIME_SRCgeneric isTrue).PAUSE_QUEUE
std_logic_vector(QUEUES-1 downto 0)
out
Issues a request to pause corresponding DMA channel.
=====
RX MFB STREAM
=====
=====
RX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
RX_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
in
Valid with SOF.
RX_MFB_QUEUE
std_logic_vector(MFB_REGIONS*max(1,log2(QUEUES))-1 downto 0)
in
ID of the packet’s DMA channel or queue.
RX_MFB_TIMESTAMP
std_logic_vector(MFB_REGIONS*TIMESTAMP_WIDTH-1 downto 0)
in
Timestamps are valid with each SOF.
RX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)
in
RX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
RX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_SRC_RDY
std_logic
in
RX_MFB_DST_RDY
std_logic
out
=====
TX MFB STREAM
=====
=====
TX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
out
Valid with SOF.
TX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)
out
TX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX_MFB_SRC_RDY
std_logic
out
TX_MFB_DST_RDY
std_logic
in
=====
MI INTERFACE
=====
=====
MI_DWR
std_logic_vector(MI_DATA_WIDTH-1 downto 0)
in
MI_ADDR
std_logic_vector(MI_ADDR_WIDTH-1 downto 0)
in
MI_BE
std_logic_vector(MI_DATA_WIDTH/8-1 downto 0)
in
Not supported!
MI_WR
std_logic
in
MI_RD
std_logic
in
MI_ARDY
std_logic
out
MI_DRD
std_logic_vector(MI_DATA_WIDTH-1 downto 0)
out
MI_DRDY
std_logic
out
Block diagram
