MFB Generator

ENTITY MFB_GENERATOR_MI32 IS

This component allows the user to generate MFB frames with some configurable options (like frame length) accessible over the MI.

The MI address space is (considering only the lowest 6 bits):

• 0x00 - Control (write 1 to start, 0 to stop)

• 0x04 - Length (set length of generated frames)

• 0x08 - Channel increment

• 0x0C - Channel minimum and maximum

• 0x10 - Dst MAC Low (lower part of destination MAC address)

• 0x14 - Dst MAC High (higher part of destination MAC address)

• 0x18 - Src MAC Low (lower part of source MAC address)

• 0x1C - Src MAC High (higher part of source MAC address)

• 0x20 - Cntr Low (lower part of counter for generated frames)

• 0x24 - Cntr High (higher part of counter for generated frames)

Register format

• Channel increment register (0x08):

+------------------------------+--------------+-------------+
| 31                         16|15           8|7           0|
+------------------------------+--------------+-------------+
| burst_size                   | CONFIG       | incr        |
+------------------------------+--------------+-------------+

• Min Max channel value register (0x0C):

+------------------------------+----------------------------+
|31                          16|15                         0|
+------------------------------+----------------------------+
| ch_max                       | ch_min                     |
+------------------------------+----------------------------+

Distribution of Ethernet frames to channels

• incr : RR increment. 0 = round-robin disable (stay on zero channel). Default 0x01

• CONFIGCONFIG[0] = channel reverse enable, others bit are reserved. Default 0x00

  : CONFIG[1] = Experimental: Enables burst mode in which the amount of burst_size

  packets are sent and the transmission is stopped until next cycle of enable of the generator occurs (that is burst is sent -> disable -> enable). NOTE: Does not work with USE_PACP_ARCH set to true

• burst_size : number of packets to begenerated before channel is changed

• ch_min : the lowest channel number for round-robin distribution. Default 0x0000

• ch_max : the highest channel number for round-robin distribution. Default 0xFFFF

Generics

Generic	Type	Default	Description
REGIONS	natural	4	number of regions in a data word
REGION_SIZE	natural	8	number of blocks in a region
BLOCK_SIZE	natural	8	number of items in a block
ITEM_WIDTH	natural	8	number of bits in an item
LENGTH_WIDTH	natural	15	the width of length signal, max 32
CHANNELS_WIDTH	natural	6	the width of channel signal, must be <= PKT_CNT_WIDTH
PKT_CNT_WIDTH	natural	32	the width of packet counter, max 64 !!
USE_PACP_ARCH	boolean	true	use Packet Planner Generator Core architecture
DEVICE	string	“STRATIX10”	FPGA device string

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RST	std_logic	in
MI_DWR	std_logic_vector(31 downto 0)	in
MI_ADDR	std_logic_vector(31 downto 0)	in
MI_BE	std_logic_vector(3 downto 0)	in	Byte enabling is not supported!
MI_RD	std_logic	in
MI_WR	std_logic	in
MI_ARDY	std_logic	out
MI_DRD	std_logic_vector(31 downto 0)	out
MI_DRDY	std_logic	out
TX_MFB_DATA	std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)	out
TX_MFB_META	std_logic_vector(REGIONS*(CHANNELS_WIDTH+LENGTH_WIDTH)-1 downto 0)	out	Contains the packet’s channel number & it’s length
TX_MFB_SOF	std_logic_vector(REGIONS-1 downto 0)	out
TX_MFB_EOF	std_logic_vector(REGIONS-1 downto 0)	out
TX_MFB_SOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)	out
TX_MFB_EOF_POS	std_logic_vector(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0)	out
TX_MFB_SRC_RDY	std_logic	out
TX_MFB_DST_RDY	std_logic	in

Distribution examples

• 0x000000: Do not distribute frames

• 0xff0001: Distribute frames to all available channels

• 0x070401: Distribute frames to channels 4 to 7

• 0xff0002: Distribute frames to all even channels (0, 2, 4, …)

• 0x050501: Send all frames to channel number 5 only