Crossbarx Output Buffer
- ENTITY MFB_CROSSBARX_OUTPUT_BUFFER IS
This component receives data through a buffer write interface. It also receives informations about Packets contained in that data and based on these informations automaticly sends the written data to output MFB interface (the Packet info is sent on separated MVB interface).
GenericsGeneric
Type
Default
Description
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Others
=====
=====
DEVICE
string
“STRATIX10”
Target Device STRATIX10, ULTRASCALE, ..
HDR_META_WIDTH
natural
12
Width of Header Metadata signal
=====
Output MVB info
=====
=====
MVB_ITEMS
natural
8
=====
Output MFB info
=====
=====
MFB_REGIONS
natural
4
MFB_REGION_SIZE
natural
2
MFB_BLOCK_SIZE
natural
8
MFB_ITEM_WIDTH
natural
16
=====
MFB metadata info
=====
=====
MFB_META_WITH_SOF
boolean
true
metadata is valid with SOF when True, or with EOF when False
MFB_META_WIDTH
natural
1
=====
Buffer data information
=====
=====
BUF_BLOCKS
natural
16
DATA_BLOCK_SIZE
natural
8
DATA_ITEM_WIDTH
natural
8
BUF_WORDS
natural
512
Number of words in buffer
CHANNELS
natural
64
Number of Channels
PKT_SIZE_MAX
natural
2**12
Maximum size of Packet (in number of Data Items)
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Clock signal relations
=====
=====
META_EQ_OUTPUT
boolean
false
CLK_META is the same as CLK_OUT
INPUT_EQ_OUTPUT
boolean
false
CLK_IN is the same as CLK_OUT
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Derived aliases
=====
=====
DATA_BLOCK_WIDTH
natural
DATA_BLOCK_SIZE*DATA_ITEM_WIDTH
BUF_BYTES
natural
BUF_WORDS*BUF_BLOCKS*DATA_BLOCK_SIZE
Port
Type
Mode
Description
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Clock and Reset
=====
=====
CLK_META
std_logic
in
Clock and Reset for Metadata interfaces
RESET_META
std_logic
in
CLK_IN
std_logic
in
Clock and Reset for Data input
RESET_IN
std_logic
in
CLK_OUT
std_logic
in
Clock and Reset for Data output
RESET_OUT
std_logic
in
=====
Buffer data interface
=====
Runs on CLK_IN
WR_ADDR
slv_array_t (BUF_BLOCKS-1 downto 0)(log2(BUF_WORDS)-1 downto 0)
in
WR_DATA
slv_array_t (BUF_BLOCKS-1 downto 0)(DATA_BLOCK_WIDTH-1 downto 0)
in
WR_IE
slv_array_t (BUF_BLOCKS-1 downto 0)(DATA_BLOCK_SIZE-1 downto 0)
in
WR_EN
std_logic_vector(BUF_BLOCKS-1 downto 0)
in
=====
Other components input interfaces
=====
Runs on CLK_OUT
RX_HDR_META
slv_array_t (MFB_REGIONS-1 downto 0)(HDR_META_WIDTH-1 downto 0)
in
RX_HDR_MFB_META
slv_array_t (MFB_REGIONS-1 downto 0)(MFB_META_WIDTH-1 downto 0)
in
RX_HDR_CHAN
slv_array_t (MFB_REGIONS-1 downto 0)(log2(CHANNELS)-1 downto 0)
in
RX_HDR_ADDR
slv_array_t (MFB_REGIONS-1 downto 0)(log2(BUF_BYTES)-1 downto 0)
in
RX_HDR_LEN
slv_array_t (MFB_REGIONS-1 downto 0)(log2(PKT_SIZE_MAX+1)-1 downto 0)
in
RX_HDR_VLD
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_HDR_SRC_RDY
std_logic
in
RX_HDR_DST_RDY
std_logic
out
=====
Other components output interfaces
=====
Runs on CLK_META
RD_PTR
std_logic_vector(log2(BUF_BYTES)-1 downto 0)
out
Current read pointer to Buffer
PKT_SENT_CHAN
slv_array_t (MFB_REGIONS-1 downto 0)(log2(CHANNELS)-1 downto 0)
out
Information about sending each packet
PKT_SENT_LEN
slv_array_t (MFB_REGIONS-1 downto 0)(log2(PKT_SIZE_MAX+1)-1 downto 0)
out
PKT_SENT_SRC_RDY
std_logic_vector(MFB_REGIONS-1 downto 0)
out
PKT_SENT_DST_RDY
std_logic
in
=====
Output MVB interface
=====
Runs on CLK_OUT
- MVB DATA contains three parts:
length (TX_MVB_LEN),
header metadata (TX_MVB_HDR_META),
channel (TX_MVB_CHANNEL)
TX_MVB_LEN
std_logic_vector(MVB_ITEMS*log2(PKT_SIZE_MAX+1)-1 downto 0)
out
TX_MVB_HDR_META
std_logic_vector(MVB_ITEMS*HDR_META_WIDTH -1 downto 0)
out
TX_MVB_CHANNEL
std_logic_vector(MVB_ITEMS*log2(CHANNELS) -1 downto 0)
out
TX_MVB_VLD
std_logic_vector(MVB_ITEMS -1 downto 0)
out
TX_MVB_SRC_RDY
std_logic
out
TX_MVB_DST_RDY
std_logic
in
=====
Output MFB interface
=====
Runs on CLK_OUT
TX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH -1 downto 0)
out
TX_MFB_SOF
std_logic_vector(MFB_REGIONS -1 downto 0)
out
TX_MFB_EOF
std_logic_vector(MFB_REGIONS -1 downto 0)
out
TX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE)) -1 downto 0)
out
TX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE)) -1 downto 0)
out
TX_MFB_SRC_RDY
std_logic
out
TX_MFB_DST_RDY
std_logic
in