MFB PIPE

ENTITY MFB_PIPE IS

Component for pipelining MFB data paths with source and destination ready signals. Compatible with Xilinx and Intel FPGAs.

Generics

Generic	Type	Default	Description
=====	Bus parameters	=====	Frame size restrictions: none
REGIONS	integer	4	any possitive value
REGION_SIZE	integer	8	any possitive value
BLOCK_SIZE	integer	8	any possitive value
ITEM_WIDTH	integer	8	any possitive value
META_WIDTH	integer	0	any possitive value
=====	Others	=====	=====
FAKE_PIPE	boolean	false
USE_DST_RDY	boolean	true
PIPE_TYPE	string	“SHREG”	“SHREG” or “REG”
DEVICE	string	“7SERIES”

Ports

Port	Type	Mode	Description
=====	Clock and Reset	=====	=====
CLK	std_logic	in
RESET	std_logic	in
=====	MFB input interface	=====	=====
RX_DATA	std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)	in
RX_META	std_logic_vector(REGIONS*META_WIDTH-1 downto 0)	in
RX_SOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)	in
RX_EOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)	in
RX_SOF	std_logic_vector(REGIONS-1 downto 0)	in
RX_EOF	std_logic_vector(REGIONS-1 downto 0)	in
RX_SRC_RDY	std_logic	in
RX_DST_RDY	std_logic	out
=====	MFB output interface	=====	=====
TX_DATA	std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)	out
TX_META	std_logic_vector(REGIONS*META_WIDTH-1 downto 0)	out
TX_SOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)	out
TX_EOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)	out
TX_SOF	std_logic_vector(REGIONS-1 downto 0)	out
TX_EOF	std_logic_vector(REGIONS-1 downto 0)	out
TX_SRC_RDY	std_logic	out
TX_DST_RDY	std_logic	in