MFB Splitter
- ENTITY MFB_SPLITTER IS
Splits RX MFB+MVB interface to two intefaces. Switches packets based on one bit SWITCH for each MVB header.
Generics
PortsGeneric
Type
Default
Description
=====
TX MVB characteristics
=====
=====
MVB_ITEMS
integer
2
number of headers
MVB_META_WIDTH
integer
2
width of each MVB meta item
=====
TX MFB characteristics
=====
=====
MFB_REGIONS
integer
2
number of regions in word
MFB_REG_SIZE
integer
1
number of blocks in region
MFB_BLOCK_SIZE
integer
8
number of items in block
MFB_ITEM_WIDTH
integer
32
width of one item (in bits)
=====
Others
=====
=====
HDR_WIDTH
integer
DMA_DOWNHDR_WIDTH
Width of each MVB item DMA_DOWNHDR_WIDTH, DMA_UPHDR_WIDTH
MVB_OUTPUT_FIFO_SIZE
integer
8
Size of mvb output FIFOXs (in words) The minimum value is 2
USE_OUTREG
boolean
true
Create output register PIPEs
DEVICE
string
“ULTRASCALE”
“ULTRASCALE”, “7SERIES”
Port
Type
Mode
Description
=====
Common interface
=====
=====
CLK
std_logic
in
RESET
std_logic
in
=====
RX interface
=====
=====
RX_MVB_HDR
std_logic_vector(MVB_ITEMS*HDR_WIDTH -1 downto 0)
in
RX_MVB_META
std_logic_vector(MVB_ITEMS*MVB_META_WIDTH-1 downto 0)
in
RX_MVB_SWITCH
std_logic_vector(MVB_ITEMS -1 downto 0)
in
output select for each header
RX_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS -1 downto 0)
in
header contains payload in MFB
RX_MVB_VLD
std_logic_vector(MVB_ITEMS -1 downto 0)
in
RX_MVB_SRC_RDY
std_logic
in
RX_MVB_DST_RDY
std_logic
out
RX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
RX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
in
RX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
RX_MFB_SRC_RDY
std_logic
in
RX_MFB_DST_RDY
std_logic
out
=====
TX interface 0
=====
=====
TX0_MVB_HDR
std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)
out
TX0_MVB_META
std_logic_vector(MVB_ITEMS*MVB_META_WIDTH-1 downto 0)
out
TX0_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX0_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX0_MVB_SRC_RDY
std_logic
out
TX0_MVB_DST_RDY
std_logic
in
TX0_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX0_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX0_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX0_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
out
TX0_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX0_MFB_SRC_RDY
std_logic
out
TX0_MFB_DST_RDY
std_logic
in
=====
TX interface 1
=====
=====
TX1_MVB_HDR
std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)
out
TX1_MVB_META
std_logic_vector(MVB_ITEMS*MVB_META_WIDTH-1 downto 0)
out
TX1_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX1_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX1_MVB_SRC_RDY
std_logic
out
TX1_MVB_DST_RDY
std_logic
in
TX1_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX1_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX1_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX1_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
out
TX1_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX1_MFB_SRC_RDY
std_logic
out
TX1_MFB_DST_RDY
std_logic
in
MFB Splitter Gen
- ENTITY MFB_SPLITTER_GEN IS
MFB+MVB bus splitter with generic number of outputs
Generics
PortsGeneric
Type
Default
Description
SPLITTER_OUTPUTS
integer
2
number of splitter outputs
=====
MVB characteristics
=====
=====
MVB_ITEMS
integer
2
number of headers
MVB_ITEM_WIDTH
integer
32
width of header
=====
MFB characteristics
=====
=====
MFB_REGIONS
integer
2
number of regions in word
MFB_REG_SIZE
integer
1
number of blocks in region
MFB_BLOCK_SIZE
integer
8
number of items in block
MFB_ITEM_WIDTH
integer
32
width of one item (in bits)
=====
Others
=====
=====
OUTPUT_FIFO_SIZE
integer
8
Size of output MVB FIFOs (in words) Minimum value is 2!
OUT_PIPE_EN
boolean
true
Output PIPE enable for all 2:1 splitters
DEVICE
string
“ULTRASCALE”
“ULTRASCALE”, “STRATIX10”,…
Port
Type
Mode
Description
=====
Common interface
=====
=====
CLK
std_logic
in
RESET
std_logic
in
=====
RX interfaces
=====
=====
RX_MVB_DATA
std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
in
RX_MVB_SWITCH
std_logic_vector(MVB_ITEMS*log2(SPLITTER_OUTPUTS)-1 downto 0)
in
output select for each header
RX_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS-1 downto 0)
in
the header is associated with a payload frame on MFB
RX_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
in
RX_MVB_SRC_RDY
std_logic
in
RX_MVB_DST_RDY
std_logic
out
RX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
RX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
in
RX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
RX_MFB_SRC_RDY
std_logic
in
RX_MFB_DST_RDY
std_logic
out
=====
TX interface
=====
=====
TX_MVB_DATA
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
out
TX_MVB_PAYLOAD
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)
out
the header is associated with a payload frame on MFB
TX_MVB_VLD
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)
out
TX_MVB_SRC_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
out
TX_MVB_DST_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
in
TX_MFB_DATA
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX_MFB_SOF
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)
out
TX_MFB_EOF
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)
out
TX_MFB_SOF_POS
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
out
TX_MFB_EOF_POS
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX_MFB_SRC_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
out
TX_MFB_DST_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
in