MVB FIFOX

ENTITY MVB_FIFOX IS

Generics

Generic	Type	Default	Description
ITEMS	natural	4	Number of MVB items in word
ITEM_WIDTH	natural	8	One MVB item width
FIFO_DEPTH	natural	512	FIFO depth, number of data words
RAM_TYPE	string	“AUTO”	Select memory implementation. Options: “LUT” - effective when ITEMS <= 64 (on Intel FPGA <= 32) “BRAM” - effective when ITEMS > 64 (on Intel FPGA > 32) “URAM” - effective when ITEMS*FIFO_WIDTH >= 288000 and FIFO_WIDTH >= 72 (URAM is only for Xilinx Ultrascale(+)) “SHIFT” - effective when ITEMS <= 16 “AUTO” - effective implementation dependent on ITEMS and DEVICE
DEVICE	string	“ULTRASCALE”	Defines what architecture is FIFO implemented on Options: “ULTRASCALE” (Xilinx) “7SERIES” (Xilinx) “ARRIA10” (Intel) “STRATIX10” (Intel)
ALMOST_FULL_OFFSET	natural	1	Determins how many data words left free when almost_full is triggered. (ITEMS - ALMOST_FULL_OFFSET)
ALMOST_EMPTY_OFFSET	natural	1	Determins how many data words present when almost_empty is triggered. (0 + ALMOST_EMPTY_OFFSET)
FAKE_FIFO	boolean	false	Disables the FIFO implementation and replaces it with straight wires.

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
RX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	in
RX_VLD	std_logic_vector(ITEMS-1 downto 0)	in
RX_SRC_RDY	std_logic	in
RX_DST_RDY	std_logic	out
TX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	out
TX_VLD	std_logic_vector(ITEMS-1 downto 0)	out
TX_SRC_RDY	std_logic	out
TX_DST_RDY	std_logic	in
STATUS	std_logic_vector(log2(FIFO_DEPTH) downto 0)	out
AFULL	std_logic	out
AEMPTY	std_logic	out

General subcomponents

• FIFOX