MVB Merge Items

ENTITY MVB_MERGE_ITEMS IS

This MVB_MERGE_ITEMS component allows to merge two different MVB streams by merging items from both streams into one item. Both input MVB streams must receive the same number of items in the same order, but they can be aligned differently. TX MVB has same item aligment as RX0 MVB input.

Generics

Generic

Type

Default

Description

RX0_ITEMS

natural

4

Number of RX0 items, same for output (TX)

RX0_ITEM_WIDTH

natural

32

RX0 item width in bits

RX1_ITEMS

natural

4

Number of RX1 items

RX1_ITEM_WIDTH

natural

16

RX1 item width in bits

TX_ITEM_WIDTH

natural

RX0_ITEM_WIDTH+RX1_ITEM_WIDTH

TX item width in bits (must be sum of RX0 and RX1)

RX0_FIFO_EN

boolean

False

Enable of FIFOX on RX0 input

FIFO_DEPTH

natural

32

Depth of FIFOs on inputs

OUTPUT_REG

boolean

False

Enable output register on TX MVB

DEVICE

string

“STRATIX10”

FPGA device string (required for FIFOs)

Ports

Port

Type

Mode

Description

CLK

std_logic

in

Clock input

RESET

std_logic

in

Reset input synchronized with CLK

RX0_DATA

std_logic_vector(RX0_ITEMS*RX0_ITEM_WIDTH-1 downto 0)

in

RX0 MVB: data word with MVB items

RX0_VLD

std_logic_vector(RX0_ITEMS-1 downto 0)

in

RX0 MVB: valid of each MVB item

RX0_SRC_RDY

std_logic

in

RX0 MVB: source ready

RX0_DST_RDY

std_logic

out

RX0 MVB: destination ready

RX1_DATA

std_logic_vector(RX1_ITEMS*RX1_ITEM_WIDTH-1 downto 0)

in

RX1 MVB: data word with MVB items

RX1_VLD

std_logic_vector(RX1_ITEMS-1 downto 0)

in

RX1 MVB: valid of each MVB item

RX1_SRC_RDY

std_logic

in

RX1 MVB: source ready

RX1_DST_RDY

std_logic

out

RX1 MVB: destination ready

TX_DATA

std_logic_vector(RX0_ITEMS*TX_ITEM_WIDTH-1 downto 0)

out

TX MVB: Data word from both inputs (concatenated)

TX_DATA0

std_logic_vector(RX0_ITEMS*RX0_ITEM_WIDTH-1 downto 0)

out

TX MVB: Data word from RX0 input

TX_DATA1

std_logic_vector(RX0_ITEMS*RX1_ITEM_WIDTH-1 downto 0)

out

TX MVB: Data word from RX1 input

TX_VLD

std_logic_vector(RX0_ITEMS-1 downto 0)

out

TX MVB: valid of each MVB item

TX_SRC_RDY

std_logic

out

TX MVB: source ready

TX_DST_RDY

std_logic

in

TX MVB: destination ready