MVB Operation

ENTITY MVB_OPERATION IS

This component enables optional transaction forking and response receiving based on RX_OP_EN. Optionally forked data are sent to TX Operation Interface and responses are received from RX Operation Interface. RX_OP_VLD vector must be same as operation received from TX_OP_VLD (no shakedown behaviour must be present in operation unit) and responses must not be reordered. When shakedown behaviour of OP unit is required, one can put SHAKEDOWN before RX Interface.

Both received data and responses are then transmitted on TX Interface.

No reordering of transactions is happening in this component. This means, when one item requires operation to be executed, whole word will be blocked and waiting for response. When no item requires execution, the word will leave the component asap. without waiting for response.

Entity architecture.

Generics

Generic	Type	Default	Description
MVB_ITEMS	natural	1	Number of MVB items in word
ITEM_WIDTH	natural	64	One MVB item width
CONSUME_ITEM_WIDTH	natural	0	Width of consumable item. When one needs to transmit some data to TX_OP interface and they are not needed later, some resources in latency FIFO will be saved by sending it as consumable item.
RSP_ITEM_WIDTH	natural	24	Operation response MVB item width
LATENCY_FIFO_EN	boolean	false	When set to true, FIFOX will be instantiated to cover latency of operation
LATENCY_FIFO_DEPTH	natural	16	Latency FIFO depth, set to, or greater than latency of operation (eg. when operation is reading from BRAM with output register, set it to > 1)
LATENCY_FIFO_RAM_TYPE	string	“AUTO”	Latency FIFO ram type. Options: “LUT” - effective when ITEMS <= 64 (on Intel FPGA <= 32) “BRAM” - effective when ITEMS > 64 (on Intel FPGA > 32) “URAM” - effective when ITEMS*FIFO_WIDTH >= 288000 and FIFO_WIDTH >= 72 (URAM is only for Xilinx Ultrascale(+)) “SHIFT” - effective when ITEMS <= 16 “AUTO” - effective implementation dependent on ITEMS and DEVICE
RX_OP_PIPE_EN	boolean	true	Enables pipe on RX_OP_RESPONSE interface
DEVICE	string	“AGILEX”	Defines what architecture is FIFO implemented on Options: “ULTRASCALE” (Xilinx) “7SERIES” (Xilinx) “ARRIA10” (Intel) “STRATIX10” (Intel)

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
=====	RX Interface	=====	Standard MVB interface
RX_DATA	std_logic_vector(MVB_ITEMS * ITEM_WIDTH - 1 downto 0)	in
RX_DATA_CONSUME	std_logic_vector(MVB_ITEMS * CONSUME_ITEM_WIDTH - 1 downto 0)	in	Data which will be consumed by operation. They are not transmitted to TX interface
RX_OP_EN	std_logic_vector(MVB_ITEMS - 1 downto 0)	in	Operation enable for each MVB item
RX_VLD	std_logic_vector(MVB_ITEMS - 1 downto 0)	in
RX_SRC_RDY	std_logic	in
RX_DST_RDY	std_logic	out
=====	TX Operation Interface	=====	Interface to unit executing the operation.
TX_OP_DATA	std_logic_vector(MVB_ITEMS * ITEM_WIDTH - 1 downto 0)	out
TX_OP_DATA_CONSUME	std_logic_vector(MVB_ITEMS * CONSUME_ITEM_WIDTH - 1 downto 0)	out
TX_OP_VLD	std_logic_vector(MVB_ITEMS - 1 downto 0)	out
TX_OP_SRC_RDY	std_logic	out
TX_OP_DST_RDY	std_logic	in
=====	RX Operation Interface	=====	Interface for receiving responses from operation unit.
RX_OP_RESPONSE	std_logic_vector(MVB_ITEMS * RSP_ITEM_WIDTH - 1 downto 0)	in
RX_OP_VLD	std_logic_vector(MVB_ITEMS - 1 downto 0)	in	Valid vector must exacly same as received from TX Operation Interface.
RX_OP_SRC_RDY	std_logic	in
RX_OP_DST_RDY	std_logic	out
=====	TX Interface	=====	Interface with previously received data and responses.
TX_DATA	std_logic_vector(MVB_ITEMS * ITEM_WIDTH - 1 downto 0)	out	Data received from RX Interface
TX_RESPONSE	std_logic_vector(MVB_ITEMS * RSP_ITEM_WIDTH - 1 downto 0)	out	Responses from operation unit
TX_RESPONSE_VLD	std_logic_vector(MVB_ITEMS - 1 downto 0)	out	Response valid, eg. operation was executed on i-th item. This vector is same as received RX_OP_EN.
TX_VLD	std_logic_vector(MVB_ITEMS - 1 downto 0)	out
TX_SRC_RDY	std_logic	out
TX_DST_RDY	std_logic	in