MVB Lookup Table
- ENTITY MVB_LOOKUP_TABLE IS
Component MVB_LOOKUP_TABLE allows to read values from the lookup table using the MVB bus. The input MVB transaction must contain the address of an entry in the lookup table. This MVB transaction will be transferred to the output in a few clock cycles, where it will additionally contain the value of the item read from the lookup table. This component allows the lookup table to be implemented using LUTRAM, BRAM and a register (LUT_DEPTH=1 only). The contents of the lookup table can be configured through a simple SW interface.
Generics
PortsGeneric
Type
Default
Description
MVB_ITEMS
natural
4
LUT_DEPTH
natural
128
LUT_WIDTH
natural
32
LUT_ARCH
string
“AUTO”
SW_WIDTH
natural
32
META_WIDTH
natural
1
OUTPUT_REG
boolean
True
DEVICE
string
“AGILEX”
Port
Type
Mode
Description
CLK
std_logic
in
RESET
std_logic
in
RX_MVB_LUT_ADDR
slv_array_t(MVB_ITEMS-1 downto 0)(max(log2(LUT_DEPTH),1)-1 downto 0)
in
RX_MVB_METADATA
slv_array_t(MVB_ITEMS-1 downto 0)(META_WIDTH-1 downto 0)
in
RX_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
in
RX_MVB_SRC_RDY
std_logic
in
RX_MVB_DST_RDY
std_logic
out
TX_MVB_LUT_DATA
slv_array_t(MVB_ITEMS-1 downto 0)(LUT_WIDTH-1 downto 0)
out
TX_MVB_LUT_ADDR
slv_array_t(MVB_ITEMS-1 downto 0)(max(log2(LUT_DEPTH),1)-1 downto 0)
out
TX_MVB_METADATA
slv_array_t(MVB_ITEMS-1 downto 0)(META_WIDTH-1 downto 0)
out
TX_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX_MVB_SRC_RDY
std_logic
out
TX_MVB_DST_RDY
std_logic
in
SW_ADDR
std_logic_vector(max(log2(LUT_DEPTH),1)-1 downto 0)
in
SW_SLICE
std_logic_vector(max(log2(LUT_WIDTH/SW_WIDTH),1)-1 downto 0)
in
SW_DIN
std_logic_vector(SW_WIDTH-1 downto 0)
in
SW_BE
std_logic_vector(SW_WIDTH/8-1 downto 0)
in
SW_WRITE
std_logic
in
SW_READ
std_logic
in
SW_DOUT
std_logic_vector(SW_WIDTH-1 downto 0)
out
SW_DOUT_VLD
std_logic
out