MVB2MFB
- ENTITY MVB2MFB IS
Component MVB2MFB converts MVB ITEMs to MFB transactions. It is possible to set different parameters for the input MVB bus and the output MFB bus. However, there are several limiting conditions, see the description of generics ports. MFB metadata are valid with each SOF.
Generics
PortsGeneric
Type
Default
Description
MVB_ITEMS
natural
4
MVB_ITEM_WIDTH
natural
536
MVB_ITEM_WIDTH must be a multiple of MFB_ITEM_WIDTH; MVB_ITEM_WIDTH must be >= MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH or MFB_ALIGNMENT must be = MFB_REGION_SIZE*MFB_BLOCK_SIZE
MFB_REGIONS
natural
4
MFB_REGION_SIZE
natural
8
MFB_BLOCK_SIZE
natural
8
MFB_ITEM_WIDTH
natural
8
MFB_ALIGNMENT
natural
MFB_REGION_SIZE*MFB_BLOCK_SIZE
Alignment of the start of MFB transactions in MFB ITEMs: Higher number => saving resources and better timing, lower number => higher transmission efficiency. MFB_ALIGNMENT must be power of two; minimum value is MFB_BLOCK_SIZE, maximum value is MFB_REGION_SIZE*MFB_BLOCK_SIZE.
META_WIDTH
natural
12
User metadata width in bits
DEVICE
string
“AGILEX”
FPGA device string (required for FIFO)
Port
Type
Mode
Description
CLK
std_logic
in
Clock input
RESET
std_logic
in
Reset input synchronized with CLK
RX_MVB_DATA
std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
in
RX_MVB_META
std_logic_vector(MVB_ITEMS*META_WIDTH-1 downto 0)
in
RX_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
in
RX_MVB_SRC_RDY
std_logic
in
RX_MVB_DST_RDY
std_logic
out
TX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX_MFB_META
std_logic_vector(MFB_REGIONS*META_WIDTH-1 downto 0)
out
MFB metadata are valid with each SOF.
TX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)
out
TX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX_MFB_SRC_RDY
std_logic
out
TX_MFB_DST_RDY
std_logic
in