FIFOX

ENTITY FIFOX IS

A universal FIFO, capable of implementation in multiple types of memories. Both DATA_WIDTH and ITEMS may be set to any value; however ITEMS has an implicit lower limit of 2 that will be automatically used if required.

This component is capable of automatic choice of implementation based on the required size and capabilities of selected DEVICE.

Delay: None of WR, DI, FULL, DO, EMPTY, STATUS, AFULL, or AEMPTY has any delay; however, written data takes at least two clock cycles before it can be read.

Generics

Generic	Type	Default	Description
DATA_WIDTH	natural	16	Data word width in bits.
ITEMS	natural	16	FIFO depth in number of data words
RAM_TYPE	string	“AUTO”	See FIFOX_RAM_TYPE
DEVICE	string	“ULTRASCALE”	Defines what architecture the FIFO is implemented on Options: “ULTRASCALE” (Xilinx) “7SERIES” (Xilinx) “ARRIA10” (Intel) “STRATIX10” (Intel) “AGILEX” (Intel)
ALMOST_FULL_OFFSET	natural	0	Determines how few data words must be left free for AFULL to be triggered. (currently_stored >= ( ITEMS - ALMOST_FULL_OFFSET)
ALMOST_EMPTY_OFFSET	natural	0	Determines how few data words must be stored for AEMPTY to be triggered. ( currently_stored <= ALMOST_EMPTY_OFFSET )
FAKE_FIFO	boolean	false	Disables the FIFO implementation and replaces it with straight wires.

TYPE FIFOX_RAM_TYPE IS

Represents the type of memory implementation used by FIFOX. Should be chosen based on the target FPGA and required size of the FIFOX

Note: this type is for documentation only; string representations of the values of this type are actually used instead.

LUT

Recommended when ITEMS ≤ 64 ( respectively ≤ 32 on Intel FPGAs)

BRAM

Recommended when ITEMS > 64 ( respectively > 32 on Intel FPGAs). Check out example1

URAM

Important

Xilinx Ultrascale(+) only!

Recommended when DATA_WIDTH ≥ 72 and ITEMS * DATA_WIDTH ≥ 288 000

SHIFT

Recommended when ITEMS ≤ 16.

AUTO

Choose an implementation automatically based on ITEMS and DEVICE.

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
=====	WRITE INTERFACE	=====	=====
DI	std_logic_vector(DATA_WIDTH-1 downto 0)	in	Data input
WR	std_logic	in	Write enable
FULL	std_logic	out	Full flag
AFULL	std_logic	out	Almost full flag
STATUS	std_logic_vector(MAX(log2(ITEMS),1) downto 0)	out	Items in memory
=====	READ INTERFACE	=====	=====
DO	std_logic_vector(DATA_WIDTH-1 downto 0)	out	Data output
RD	std_logic	in	Data on DO were read
EMPTY	std_logic	out	Empty flag
AEMPTY	std_logic	out	Almost empty flag

Block diagram

TODO- Přidat blokový diagram komponenty FIFOX

Verification

Verification is coverage oriented. There is code coverage turned on. The code coverage report can be generated by uncommenting one line in top_level.fdo. Both input and output interfaces of component are connected by MVB interfaces to the verification environment. The scoreboard checks that the data that are written into component are readed in correct order at output interface.

Verification block diagram

There are 3 tests. The first 2 are most random and are designed to verify correct functionality in classic use. The 3th one is designed to check functionality when data are more often written and less often readed.