MVB Channel Router

ENTITY MVB_CHANNEL_ROUTER_MI IS

This component works as a simple configurable routing table. It is primarily used for basic routing of Ethernet frames to selected DMA channels. You can use generics to set three modes of default behavior (see DEFAULT_MODE generic). The user can change the routing rules through the MI interface.

MI address space and register format:

Address space: SRC -> DST channel distribution table:
   0x000000: Source channel 0 round-robin distr. control
   0x000004: Source channel 1 round-robin distr. control
   0x000008: Source channel 2 round-robin distr. control
   ....

 Round-robin distribution control register format:
 31             23              15             7           0
+----------------------------------------------------------+
|     RSVD     |     ch_max    |    ch_min    |    incr    |
+----------------------------------------------------------+
Controls distribution of ethernet frames received from network to DMA channels
  incr   : RR increment. 0 = round-robin disable (stay on source channel). Default 0x0
  ch_min : low DMA channel limit for round-robin distribution. Default 0x0
  ch_max : high DMA channel limit for round-robin distribution. Default 0x0

Examples:
   0x000000: Do not distribute frames - frame from Eth chan N is routed to DMA chan N
   0xff0001: Distribute frames to all available DMA channels
   0x070401: Distribute frames to DMA channels 4 to 7
   0xff0002: Distribute frames to even DMA channels
   0x050501: Send all frames to DMA channel 5 only

Channel number calculation:

The channel number calculation method differs for OPT_MODE on and off. In OPT_MODE = false mode (default), the destination channel number is calculated according to the following algorithm independently for each source channel:

reset: ch_cnt = ch_min;

ch_out = ch_cnt;
ch_next = ch_cnt + incr
if ((ch_next <= ch_max) and (ch_next < DST_CHANNELS) and (ch_next >= ch_min)):
    ch_cnt = ch_cnt + incr;
else:
    ch_cnt = ch_min;

In OPT_MODE = true mode, the destination channel number is calculated according to the following algorithm independently for each source channel:

reset: ch_cnt = 0;

ch_diff = ch_max - ch_min;
ch_out = ch_cnt + ch_min;
ch_cnt = (ch_cnt + incr) and (ch_diff);

Generics

Generic	Type	Default	Description
ITEMS	natural	4	MVB parameters: number of items in word
ITEM_WIDTH	natural	32	MVB parameters: width of item in bits
SRC_CHANNELS	natural	4	Total number of source channels, max value = DST_CHANNELS
DST_CHANNELS	natural	16	Total number of destination channels, max value = 256
DEFAULT_MODE	natural	0	Default routing mode: 0 = stay on source channel; 1 = each SRC channel is routed to all DST channels (round-robin); 2 = all DST channels are divided into separate groups for each SRC channel, there is round-robin routing in each group (SRC channel);
OPT_MODE	boolean	False	Optimized mode for better timing (best for high ITEMS) with limited configuration: (ch_max-ch_min+1) must be power of two
MI_DATA_WIDTH	natural	32	MI parameters: width of data signals, min value is 32
MI_ADDR_WIDTH	natural	32	MI parameters: width of address signal
DEVICE	string	“ULTRASCALE”	Name of FPGA device

Ports

Port	Type	Mode	Description
=====	CLOCK AND RESET	=====	=====
CLK	std_logic	in	clock input
RESET	std_logic	in	reset input synchronized with CLK, minimum length is 4 cycles
=====	MI INTERFACE	=====	=====
MI_DWR	std_logic_vector(MI_DATA_WIDTH-1 downto 0)	in	MI bus: data from master to slave (write data)
MI_ADDR	std_logic_vector(MI_ADDR_WIDTH-1 downto 0)	in	MI bus: slave address
MI_BE	std_logic_vector((MI_DATA_WIDTH/8)-1 downto 0)	in	MI bus: byte enable, not supported in this component!
MI_RD	std_logic	in	MI bus: read request
MI_WR	std_logic	in	MI bus: write request
MI_ARDY	std_logic	out	MI bus: ready of slave module
MI_DRD	std_logic_vector(MI_DATA_WIDTH-1 downto 0)	out	MI bus: data from slave to master (read data)
MI_DRDY	std_logic	out	MI bus: valid of MI_DRD data signal
=====	INPUT MVB INTERFACE	=====	=====
RX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	in	RX MVB: data word with MVB items
RX_CHANNEL	std_logic_vector(ITEMS*log2(SRC_CHANNELS)-1 downto 0)	in	RX MVB: channel word with MVB items (SRC channel per each MVB item)
RX_VLD	std_logic_vector(ITEMS-1 downto 0)	in	RX MVB: valid of each MVB item
RX_SRC_RDY	std_logic	in	RX MVB: source ready
RX_DST_RDY	std_logic	out	RX MVB: destination ready
=====	OUTPUT MVB INTERFACE	=====	=====
TX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	out	TX MVB: data word with MVB items
TX_CHANNEL	std_logic_vector(ITEMS*log2(DST_CHANNELS)-1 downto 0)	out	TX MVB: channel word with MVB items (DST channel per each MVB item)
TX_VLD	std_logic_vector(ITEMS-1 downto 0)	out	TX MVB: valid of each MVB item
TX_SRC_RDY	std_logic	out	TX MVB: source ready
TX_DST_RDY	std_logic	in	TX MVB: destination ready