Software Manager
- ENTITY TX_DMA_SW_MANAGER IS
This component provides control interface for TX DMA Calypte controller. It contains MI configuration registers which allows acces from the SW to control some behavior of the controller or to read status information. Each channel has its own set of registers. The component serves as a master when start/stop of a specific channel needs to be done. When start/stop of multiple channels is requested, the channels are started/stopped one after anoter, not all at once.
Generics
PortsGeneric
Type
Default
Description
DEVICE
string
“STRATIX10”
Traget device
CHANNELS
natural
8
Total number of DMA Channels within this DMA Endpoint
RECV_PKT_CNT_WIDTH
natural
64
Actual width of packet and byte counters
RECV_BTS_CNT_WIDTH
natural
64
DISC_PKT_CNT_WIDTH
natural
64
DISC_BTS_CNT_WIDTH
natural
64
DATA_POINTER_WIDTH
natural
14
Width of the pointer to data and DMA header buffers signify depth of the internal buffers in the CHANNEL_CORE
DMA_HDR_POINTER_WIDTH
natural
9
PKT_SIZE_MAX
natural
2**12
Maximum size of a packet (in bytes)
Defines width of Packet length signals.
MI_WIDTH
natural
32
Width of MI bus
Port
Type
Mode
Description
=====
Clock and Reset
=====
=====
CLK
std_logic
in
RESET
std_logic
in
=====
MI interface for SW access
=====
=====
MI_ADDR
std_logic_vector(MI_WIDTH-1 downto 0)
in
MI_DWR
std_logic_vector(MI_WIDTH-1 downto 0)
in
MI_BE
std_logic_vector(MI_WIDTH/8-1 downto 0)
in
MI_RD
std_logic
in
MI_WR
std_logic
in
MI_DRD
std_logic_vector(MI_WIDTH-1 downto 0)
out
MI_ARDY
std_logic
out
MI_DRDY
std_logic
out
=====
Input packet discart/sent counter interface
=====
=====
PKT_SENT_CHAN
std_logic_vector(log2(CHANNELS)-1 downto 0)
in
PKT_SENT_INC
std_logic
in
PKT_SENT_BYTES
std_logic_vector(log2(PKT_SIZE_MAX+1)-1 downto 0)
in
PKT_DISCARD_CHAN
std_logic_vector(log2(CHANNELS)-1 downto 0)
in
PKT_DISCARD_INC
std_logic
in
PKT_DISCARD_BYTES
std_logic_vector(log2(PKT_SIZE_MAX+1)-1 downto 0)
in
=====
Channel status interface
=====
=====
START_REQ_CHAN
std_logic_vector(log2(CHANNELS)-1 downto 0)
out
START_REQ_VLD
std_logic
out
START_REQ_ACK
std_logic
in
STOP_REQ_CHAN
std_logic_vector(log2(CHANNELS)-1 downto 0)
out
STOP_REQ_VLD
std_logic
out
STOP_REQ_ACK
std_logic
in
ENABLED_CHAN
std_logic_vector(CHANNELS-1 downto 0)
out
general vector of all channels with their activity
HDP_WR_CHAN
std_logic_vector(log2(CHANNELS)-1 downto 0)
in
Hardware pointers writing interface
HDP_WR_DATA
std_logic_vector(DATA_POINTER_WIDTH-1 downto 0)
in
HDP_WR_EN
std_logic
in
HHP_WR_CHAN
std_logic_vector(log2(CHANNELS)-1 downto 0)
in
HHP_WR_DATA
std_logic_vector(DMA_HDR_POINTER_WIDTH-1 downto 0)
in
HHP_WR_EN
std_logic
in