TX DMA Calypte

ENTITY TX_DMA_CALYPTE IS

Warning

The Completer Completion interface is not supported yet. Calypte Controller supports only Memory Write PCIe transactions.

This is the transmitting part of the DMA Calypte core. TX direction behaves similarly to the RX DMA Calypte. Data buffers are provided in the hardware to which the data can be stored. The frames are output on the USR_TX_ side and PCI Express transactions are accepted on the PCIE_CQ_ side. Output frame can constist out of multiple PCIe transactions. Each such frame is delimited by the DMA header which provides the size of the frame as well as the channel to which the frame is designated and an address of the first byte of the frame. PCIe transactions can be send on the unsorted series of adresses. The DMA header then serves as delimiting block where, after its acceptance, the frame on the output is read continuously from the address of the first byte. The block scheme of the TX DMA Calypte controller is provided in the following figure:

Generics

Generic	Type	Default	Description
DEVICE	string	“ULTRASCALE”
MI_WIDTH	natural	32
=====	Output interface to the FPGA user logic	=====	=====
USR_TX_MFB_REGIONS	natural	1
USR_TX_MFB_REGION_SIZE	natural	4
USR_TX_MFB_BLOCK_SIZE	natural	8
USR_TX_MFB_ITEM_WIDTH	natural	8
=====	Input PCIe interface (Completer Request)	=====	=====
PCIE_CQ_MFB_REGIONS	natural	1
PCIE_CQ_MFB_REGION_SIZE	natural	1
PCIE_CQ_MFB_BLOCK_SIZE	natural	8
PCIE_CQ_MFB_ITEM_WIDTH	natural	32
=====	Output PCIe interface (Completer Completion) MFB setting	=====	=====
PCIE_CC_MFB_REGIONS	natural	1
PCIE_CC_MFB_REGION_SIZE	natural	1
PCIE_CC_MFB_BLOCK_SIZE	natural	8
PCIE_CC_MFB_ITEM_WIDTH	natural	32
=====	Setting of internal components	=====	=====
DATA_POINTER_WIDTH	natural	14	Pointer width for data and hdr buffers. The data pointer points to bytes of the packet. The header pointer points to the header of a current packet.
DMA_HDR_POINTER_WIDTH	natural	11
CHANNELS	natural	32	Set the number of DMA channels, each channel has its separate buffer
=====	Others	=====	=====
CNTRS_WIDTH	natural	64	Set the width of counters of packets for each channel which are there to provide some entry level statistics.
HDR_META_WIDTH	natural	24	Width of the metadata in bits which are stored in the DMA header.
ST_SP_DBG_SIGNAL_W	natural	4
PKT_SIZE_MAX	natural	2**11	Size of the largest packets that can be transmitted on the USR_TX_MFB interface.

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
=====	User MFB signals	=====	=====
USR_TX_MFB_META_PKT_SIZE	std_logic_vector(log2(PKT_SIZE_MAX + 1) -1 downto 0)	out
USR_TX_MFB_META_CHAN	std_logic_vector(log2(CHANNELS) -1 downto 0)	out
USR_TX_MFB_META_HDR_META	std_logic_vector(HDR_META_WIDTH -1 downto 0)	out
USR_TX_MFB_DATA	std_logic_vector(USR_TX_MFB_REGIONS*USR_TX_MFB_REGION_SIZE*USR_TX_MFB_BLOCK_SIZE*USR_TX_MFB_ITEM_WIDTH-1 downto 0)	out
USR_TX_MFB_SOF	std_logic_vector(USR_TX_MFB_REGIONS -1 downto 0)	out
USR_TX_MFB_EOF	std_logic_vector(USR_TX_MFB_REGIONS -1 downto 0)	out
USR_TX_MFB_SOF_POS	std_logic_vector(USR_TX_MFB_REGIONS*max(1, log2(USR_TX_MFB_REGION_SIZE)) -1 downto 0)	out
USR_TX_MFB_EOF_POS	std_logic_vector(USR_TX_MFB_REGIONS*max(1, log2(USR_TX_MFB_REGION_SIZE*USR_TX_MFB_BLOCK_SIZE)) -1 downto 0)	out
USR_TX_MFB_SRC_RDY	std_logic	out
USR_TX_MFB_DST_RDY	std_logic	in
=====	PCIe Completer Request MFB interface	=====	Accepts PCIe write and read requests
PCIE_CQ_MFB_DATA	std_logic_vector(PCIE_CQ_MFB_REGIONS*PCIE_CQ_MFB_REGION_SIZE*PCIE_CQ_MFB_BLOCK_SIZE*PCIE_CQ_MFB_ITEM_WIDTH-1 downto 0)	in
PCIE_CQ_MFB_META	std_logic_vector(PCIE_CQ_META_WIDTH -1 downto 0)	in
PCIE_CQ_MFB_SOF	std_logic_vector(PCIE_CQ_MFB_REGIONS -1 downto 0)	in
PCIE_CQ_MFB_EOF	std_logic_vector(PCIE_CQ_MFB_REGIONS -1 downto 0)	in
PCIE_CQ_MFB_SOF_POS	std_logic_vector(PCIE_CQ_MFB_REGIONS*max(1, log2(PCIE_CQ_MFB_REGION_SIZE)) -1 downto 0)	in
PCIE_CQ_MFB_EOF_POS	std_logic_vector(PCIE_CQ_MFB_REGIONS*max(1, log2(PCIE_CQ_MFB_REGION_SIZE*PCIE_CQ_MFB_BLOCK_SIZE)) -1 downto 0)	in
PCIE_CQ_MFB_SRC_RDY	std_logic	in
PCIE_CQ_MFB_DST_RDY	std_logic	out
=====	PCIe Completer Completion MFB interface	=====	Transmits responses to read requests received on the CQ interface
PCIE_CC_MFB_DATA	std_logic_vector(PCIE_CC_MFB_REGIONS*PCIE_CC_MFB_REGION_SIZE*PCIE_CC_MFB_BLOCK_SIZE*PCIE_CC_MFB_ITEM_WIDTH-1 downto 0)	out
PCIE_CC_MFB_META	std_logic_vector(PCIE_CC_META_WIDTH -1 downto 0)	out
PCIE_CC_MFB_SOF	std_logic_vector(PCIE_CC_MFB_REGIONS -1 downto 0)	out
PCIE_CC_MFB_EOF	std_logic_vector(PCIE_CC_MFB_REGIONS -1 downto 0)	out
PCIE_CC_MFB_SOF_POS	std_logic_vector(PCIE_CC_MFB_REGIONS*max(1, log2(PCIE_CC_MFB_REGION_SIZE)) -1 downto 0)	out
PCIE_CC_MFB_EOF_POS	std_logic_vector(PCIE_CC_MFB_REGIONS*max(1, log2(PCIE_CC_MFB_REGION_SIZE*PCIE_CC_MFB_BLOCK_SIZE)) -1 downto 0)	out
PCIE_CC_MFB_SRC_RDY	std_logic	out
PCIE_CC_MFB_DST_RDY	std_logic	in
=====	Debugging signals	=====	=====
ST_SP_DBG_CHAN	std_logic_vector(log2(CHANNELS) -1 downto 0)	out
ST_SP_DBG_META	std_logic_vector(ST_SP_DBG_SIGNAL_W -1 downto 0)	out
=====	Control MI bus	=====	=====
MI_ADDR	std_logic_vector(MI_WIDTH -1 downto 0)	in
MI_DWR	std_logic_vector(MI_WIDTH -1 downto 0)	in
MI_BE	std_logic_vector(MI_WIDTH/8 -1 downto 0)	in
MI_RD	std_logic	in
MI_WR	std_logic	in
MI_DRD	std_logic_vector(MI_WIDTH -1 downto 0)	out
MI_ARDY	std_logic	out
MI_DRDY	std_logic	out

Specific subcomponents

• Metadata Extractor
• Channel Start/stop control
• Packet Dispatcher
• Transaction buffer
• Software Manager

General subcomponents

• MVB FIFOX

UVM Verification

Verification Plan

TODO:

Coverage Mesure

There is five test in Multiver script.

coverage

conf name	base	full speed	merge
default	75.3494%	74.9002%	75.5762%
4_channels	76.4729%	76.4729%	76.4729%
8_channels, min_pcie_frames	77.6599%	77.3954%	77.6599%
buff_size_small	76.2113%	75.7632%	76.4380%
buff_size_large	75.3069%	74.8577%	755337%

Delay is mesure only for full spead test. Which allweys accept output from DUT. Delay represents how many nanoseconds take to go through DMA Calypte.

delay

conf name	min	max	average	standard deviation
defaulit	28ns	500ns	175ns	83ns
4_channels	28ns	816ns	183ns	97ns
8_channels, min_pcie_frames	24ns	944ns	192ns	111ns
buff_size_small	28ns	500ns	175ns	83ns
buff_size_big	28ns	500ns	175ns	83ns