PCIE Header parsing/deparsing
- ENTITY PCIE_RQ_HDR_GEN IS
The Purpose of this component is to fill PCIE RQ header.
Generics
PortsGeneric
Type
Default
Description
DEVICE
string
“STRATIX10”
Target device: “AGILEX”, “STRATIX10”, “7SERIES”, “ULTRASCALE”
Port
Type
Mode
Description
=====
RQ interface
=====
=====
IN_ADDRESS
std_logic_vector(62-1 downto 0)
in
Global address in bytes (address is aligned in DWORD)
IN_VFID
std_logic_vector(8-1 downto 0)
in
Virtual Function ID
IN_TAG
std_logic_vector(10-1 downto 0)
in
Tag (in case of INTEL contains: TAG_8, TAG_9, TAG, others there is “00”, TAG)
IN_DW_CNT
std_logic_vector(11-1 downto 0)
in
Length in DWORDS
IN_ATTRIBUTES
std_logic_vector(3-1 downto 0)
in
Contains snoop (bit 0), relaxed (bit 1) and ID based ordering bit (bit 2)
IN_FBE
std_logic_vector(4-1 downto 0)
in
First Byte Enable (Intel only)
IN_LBE
std_logic_vector(4-1 downto 0)
in
Last Byte Enable (Intel only)
IN_ADDR_LEN
std_logic
in
Address length type, supported are: 1 - 64-DW address 0 - 32-DW address
IN_REQ_TYPE
std_logic
in
Type of request, supported types are: 1 - write 0 - read
=====
Requester HEADER Output interface
=====
=====
OUT_HEADER
std_logic_vector(128-1 downto 0)
out
PCIE RQ header
- ENTITY PCIE_CC_HDR_GEN IS
The Purpose of this component is to fill PCIE CC header.
Generics
PortsGeneric
Type
Default
Description
DEVICE
string
“STRATIX10”
Target device: “AGILEX”, “STRATIX10”, “7SERIES”, “ULTRASCALE”
Port
Type
Mode
Description
=====
CC interface (same fo both)
=====
=====
IN_LOWER_ADDR
std_logic_vector(7-1 downto 0)
in
Lower address
IN_BYTE_CNT
std_logic_vector(13-1 downto 0)
in
Length in bytes (For Intel, only 12 bits are valid)
IN_DW_CNT
std_logic_vector(11-1 downto 0)
in
Length in DWORDS
IN_COMP_ST
std_logic_vector(3-1 downto 0)
in
Completition Status
IN_REQ_ID
std_logic_vector(16-1 downto 0)
in
Request ID
IN_TAG
std_logic_vector(10-1 downto 0)
in
Tag (in case of INTEL contains TAG_8, TAG_9, TAG, others there is “00”, TAG)
IN_TC
std_logic_vector(3-1 downto 0)
in
Transaction Class
IN_ATTRIBUTES
std_logic_vector(3-1 downto 0)
in
Contains snoop, relaxed and ID based ordering bit
IN_ADDRESS_TYPE
std_logic_vector(2-1 downto 0)
in
Global address type
IN_META_FUNC_ID
std_logic_vector(8-1 downto 0)
in
Meta function ID
IN_BUS_NUM
std_logic_vector(8-1 downto 0)
in
Bus number
COMP_WITH_DATA
std_logic
in
Type of completition: 1 - Completition with data 0 - completition without data
=====
Completer HEADER Output interface
=====
=====
OUT_HEADER
std_logic_vector(96-1 downto 0)
out
PCIE CC header
- ENTITY PCIE_RC_HDR_DEPARSER IS
The Purpose of this component is to deparse PCIE RC header.
Generics
PortsGeneric
Type
Default
Description
DEVICE
string
“STRATIX10”
Target device: “AGILEX”, “STRATIX10”, “7SERIES”, “ULTRASCALE”
Port
Type
Mode
Description
=====
RC interface
=====
=====
OUT_LOW_ADDR
std_logic_vector(12-1 downto 0)
out
Lower address
OUT_COMPLETE
std_logic
out
Complete status
OUT_DW_CNT
std_logic_vector(11-1 downto 0)
out
Length in DWORDS
OUT_TAG
std_logic_vector(10-1 downto 0)
out
Tag (in case of INTEL contains TAG_8, TAG_9, TAG, others there is “00”, TAG)
OUT_BYTE_CNT
std_logic_vector(13-1 downto 0)
out
Length in bytes (For Intel, only 12 bits are valid)
OUT_ATTRIBUTES
std_logic_vector(3-1 downto 0)
out
Contains snoop (bit 0), relaxed (bit 1) and ID based ordering bit (bit 2)
OUT_COMP_ST
std_logic_vector(3-1 downto 0)
out
Completition Status
=====
Completer HEADER Input interface
=====
=====
IN_HEADER
std_logic_vector(96-1 downto 0)
in
PCIE RC header
- ENTITY PCIE_CQ_HDR_DEPARSER IS
The Purpose of this component is to deparse PCIE CQ header.
Generics
PortsGeneric
Type
Default
Description
DEVICE
string
“STRATIX10”
Target device: “AGILEX”, “STRATIX10”, “7SERIES”, “ULTRASCALE”
CQUSER_WIDTH
natural
183
width of CQ user word in bits (Supported value are 88, 85 and 183)
Port
Type
Mode
Description
=====
CQ interface (same for both)
=====
=====
OUT_TAG
std_logic_vector(10-1 downto 0)
out
Tag (in case of INTEL contains TAG_8, TAG_9, TAG, others there is “00”, TAG)
OUT_ADDRESS
std_logic_vector(64-1 downto 0)
out
Global address in bytes (address is aligned to DWORD)
OUT_REQ_ID
std_logic_vector(16-1 downto 0)
out
Request ID
OUT_TC
std_logic_vector(3-1 downto 0)
out
Transaction Class
OUT_DW_CNT
std_logic_vector(11-1 downto 0)
out
Length in DWORDS
OUT_ATTRIBUTES
std_logic_vector(3-1 downto 0)
out
Contains snoop, relaxed and ID based ordering bit
OUT_FBE
std_logic_vector(4-1 downto 0)
out
First Byte Enable
OUT_LBE
std_logic_vector(4-1 downto 0)
out
Last Byte Enable
OUT_ADDRESS_TYPE
std_logic_vector(2-1 downto 0)
out
Global address type
OUT_TARGET_FUNC
std_logic_vector(8-1 downto 0)
out
Target function (META_FUNC_ID)
OUT_BAR_ID
std_logic_vector(3-1 downto 0)
out
BAR ID
OUT_BAR_APERTURE
std_logic_vector(6-1 downto 0)
out
BAR APERTURE
OUT_ADDR_LEN
std_logic
out
Address length type, supported are: 1 - 64-DW address 0 - 32-DW address
OUT_REQ_TYPE
std_logic_vector(4-1 downto 0)
out
Type of request, supported types are: 0000 - others 0001 - read 0010 - write 0100 - msg 1000 - msgd
=====
Completer HEADER Input interface
=====
=====
IN_AXI_TUSER
std_logic_vector(CQUSER_WIDTH-1 downto 0)
in
PCIE AXI TUSER signal
IN_HEADER
std_logic_vector(128-1 downto 0)
in
PCIE CQ header
IN_FBE
std_logic_vector(4-1 downto 0)
in
First Byte Enable
IN_LBE
std_logic_vector(4-1 downto 0)
in
Last Byte Enable
IN_INTEL_META
std_logic_vector(17-1 downto 0)
in
PCIE CQ header META, contains: BAR_APERTURE, BAR_ID, TARGET_FUNC