DSP Comparator

ENTITY DSP_COMPARATOR IS

This is a comparator that can use DSP bloks on different Devices but can also be implemented in common logic.

Note

Default and recommended latency for comparator using DSPs is 2 clock cycles, latency of 1 clock cycle is achieved when input registers are disabled.

Generics

Generic	Type	Default	Description
INPUT_DATA_WIDTH	natural	25	The width of inputs; maximum width of 25 bits applies only in modes “>= “ or “<= “ when using DSP blocks, “unlimited” in other cases
INPUT_REGS_EN	boolean	true	Enable input registers
MODE	string	“>= “	This option allows user to choose the function of the comparator (the space after “>=” or “<=” is necessary!): “><=” is the default mode which outputs results as specified above the RESULT port “>= “ outputs result in form of ‘11’ if the 1st number is larger or equal than the 2nd number, else ‘00’ - in this mode, only one DSP block is used (when enabled) “<= “ outputs result in form of ‘11’ if the 1st number is smaller or equal than the 2nd number, else ‘00’ - in this mode, only one DSP block is used (when enabled)
DSP_ENABLE	boolean	true	Set True to use DSP(s) for the comparator
DEVICE	string	“AGILEX”	Target FPGA, the allowed options are: “STRATIX10” “AGILEX” “ULTRASCALE” “7SERIES”

Ports

Port	Type	Mode	Description
CLK	std_logic	in
CLK_EN	std_logic	in
RESET	std_logic	in
INPUT_1	std_logic_vector(INPUT_DATA_WIDTH-1 downto 0)	in	The 1st number for comparison
INPUT_2	std_logic_vector(INPUT_DATA_WIDTH-1 downto 0)	in	The 2nd number for comparison
RESULT	std_logic_vector(1 downto 0)	out	The final value of the comparator, the RESULT will be: “01” (1 in dec) when the 1st number (INPUT_1) > 2nd number (INPUT_2) - applies only for mode “><=” “10” (2 in dec) when the 2nd number (INPUT_2) > 1st number (INPUT_1) - applies only for mode “><=” “00” when both numbers are equal - applies only for mode “><=”