MI Pipe

ENTITY MI_PIPE IS

Wrapper over generic Pipe (comp/base/misc/pipe) for MI interface.

Generics

Generic	Type	Default	Description
DATA_WIDTH	integer	32
ADDR_WIDTH	integer	32
META_WIDTH	integer	2
PIPE_TYPE	string	“SHREG”	Type of the PIPEs implementation: “SHREG” Pipe implemented as shift register, optimization of mapping shreg on Xilinx FPGA can be set using OPT generic “REG” Two-stage pipe created from two registers + 1 MUX, better on wide buses and on Intel/Altera devices
USE_OUTREG	boolean	false	Only for PIPE_TYPE = “SHREG”!
FAKE_PIPE	boolean	false	wires only (to disable pipe easily)
DEVICE	string	“7SERIES”

Ports

Port	Type	Mode	Description
=====	Common interface	=====	=====
CLK	std_logic	in
RESET	std_logic	in
=====	Input MI interface	=====	=====
IN_DWR	std_logic_vector(DATA_WIDTH-1 downto 0)	in
IN_MWR	std_logic_vector(META_WIDTH-1 downto 0)	in
IN_ADDR	std_logic_vector(ADDR_WIDTH-1 downto 0)	in
IN_BE	std_logic_vector(DATA_WIDTH/8-1 downto 0)	in
IN_RD	std_logic	in
IN_WR	std_logic	in
IN_ARDY	std_logic	out
IN_DRD	std_logic_vector(DATA_WIDTH-1 downto 0)	out
IN_DRDY	std_logic	out
=====	Output MI interface	=====	=====
OUT_DWR	std_logic_vector(DATA_WIDTH-1 downto 0)	out
OUT_MWR	std_logic_vector(META_WIDTH-1 downto 0)	out
OUT_ADDR	std_logic_vector(ADDR_WIDTH-1 downto 0)	out
OUT_BE	std_logic_vector(DATA_WIDTH/8-1 downto 0)	out
OUT_RD	std_logic	out
OUT_WR	std_logic	out
OUT_ARDY	std_logic	in
OUT_DRD	std_logic_vector(DATA_WIDTH-1 downto 0)	in
OUT_DRDY	std_logic	in