Transaction buffer
- ENTITY TX_DMA_PCIE_TRANS_BUFFER IS
This component instantiaties data buffers for all channels. Internally, the component constists of Block RAMs. This component has the largest footprint since data are stored by bytes for every channel. The component behaves as quasi buffer to which data can by written with the resolution to DWords and read with the resolution to bytes, i.e. as a RAM with different widths of addresses for each port.
Generics
PortsGeneric
Type
Default
Description
DEVICE
string
“ULTRASCALE”
CHANNELS
natural
8
Total number of DMA Channels within this DMA Endpoint
=====
Input PCIe interface parameters
=====
=====
MFB_REGIONS
natural
1
MFB_REGION_SIZE
natural
1
MFB_BLOCK_SIZE
natural
8
MFB_ITEM_WIDTH
natural
32
POINTER_WIDTH
natural
16
Determines the number of bytes that can be stored in the buffer.
Port
Type
Mode
Description
CLK
std_logic
in
RESET
std_logic
in
=====
Input MFB bus (quasi writing interface)
=====
=====
PCIE_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
PCIE_MFB_META
std_logic_vector((MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH)/8+log2(CHANNELS)+62+1-1 downto 0)
in
PCIE_MFB_SOF
std_logic_vector(MFB_REGIONS -1 downto 0)
in
PCIE_MFB_EOF
std_logic_vector(MFB_REGIONS -1 downto 0)
in
PCIE_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1, log2(MFB_REGION_SIZE)) -1 downto 0)
in
PCIE_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1, log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE)) -1 downto 0)
in
PCIE_MFB_SRC_RDY
std_logic
in
PCIE_MFB_DST_RDY
std_logic
out
=====
Output reading interface
=====
Similar to BRAM block.
RD_CHAN
std_logic_vector(log2(CHANNELS) -1 downto 0)
in
RD_DATA
std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
RD_ADDR
std_logic_vector(POINTER_WIDTH -1 downto 0)
in
RD_EN
std_logic
in