RX DMA Calypte

This is receiving part of the DMA Calypte core. Simple block scheme is provided in the following figure:

ENTITY RX_DMA_CALYPTE IS

Generics

Generic	Type	Default	Description
DEVICE	string	“ULTRASCALE”
MI_WIDTH	natural	32	Width of MI bus
USER_RX_MFB_REGIONS	natural	1	User Logic MFB configuration
USER_RX_MFB_REGION_SIZE	natural	8
USER_RX_MFB_BLOCK_SIZE	natural	8
USER_RX_MFB_ITEM_WIDTH	natural	8
PCIE_UP_MFB_REGIONS	natural	2	PCIe MFB configuration
PCIE_UP_MFB_REGION_SIZE	natural	1
PCIE_UP_MFB_BLOCK_SIZE	natural	8
PCIE_UP_MFB_ITEM_WIDTH	natural	32
CHANNELS	natural	8	Total number of DMA Channels within this DMA Endpoint
POINTER_WIDTH	natural	16	Width of Software and Hardware Descriptor/Header Pointer Defines width of signals used for these values in DMA Module Affects logic complexity Maximum value: 32 (restricted by size of pointer MI registers)
SW_ADDR_WIDTH	natural	64	Width of RAM address
CNTRS_WIDTH	natural	64	Actual width of packet and byte counters
HDR_META_WIDTH	natural	24
PKT_SIZE_MAX	natural	2**16 - 1	Maximum size of a packet (in bytes). Defines width of Packet length signals. Maximum allowed value is 2**16 - 1
TRBUF_FIFO_EN	boolean	FALSE

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
=====	MI interface for SW access	=====	=====
MI_ADDR	std_logic_vector(MI_WIDTH-1 downto 0)	in
MI_DWR	std_logic_vector(MI_WIDTH-1 downto 0)	in
MI_BE	std_logic_vector(MI_WIDTH/8-1 downto 0)	in
MI_RD	std_logic	in
MI_WR	std_logic	in
MI_DRD	std_logic_vector(MI_WIDTH-1 downto 0)	out
MI_ARDY	std_logic	out
MI_DRDY	std_logic	out
=====	MFB input interface	=====	=====
USER_RX_MFB_META_HDR_META	std_logic_vector(HDR_META_WIDTH-1 downto 0)	in
USER_RX_MFB_META_CHAN	std_logic_vector(log2(CHANNELS)-1 downto 0)	in
USER_RX_MFB_META_PKT_SIZE	std_logic_vector(log2(PKT_SIZE_MAX+1)-1 downto 0)	in
USER_RX_MFB_DATA	std_logic_vector(USER_RX_MFB_REGIONS*USER_RX_MFB_REGION_SIZE*USER_RX_MFB_BLOCK_SIZE*USER_RX_MFB_ITEM_WIDTH-1 downto 0)	in
USER_RX_MFB_SOF	std_logic_vector(USER_RX_MFB_REGIONS - 1 downto 0)	in
USER_RX_MFB_EOF	std_logic_vector(USER_RX_MFB_REGIONS - 1 downto 0)	in
USER_RX_MFB_SOF_POS	std_logic_vector(USER_RX_MFB_REGIONS*max(1, log2(USER_RX_MFB_REGION_SIZE))-1 downto 0)	in
USER_RX_MFB_EOF_POS	std_logic_vector(USER_RX_MFB_REGIONS*max(1, log2(USER_RX_MFB_REGION_SIZE*USER_RX_MFB_BLOCK_SIZE))-1 downto 0)	in
USER_RX_MFB_SRC_RDY	std_logic	in
USER_RX_MFB_DST_RDY	std_logic	out
=====	MFB output interface	=====	=====
PCIE_UP_MFB_DATA	std_logic_vector(PCIE_UP_MFB_REGIONS*PCIE_UP_MFB_REGION_SIZE*PCIE_UP_MFB_BLOCK_SIZE*PCIE_UP_MFB_ITEM_WIDTH-1 downto 0)	out
PCIE_UP_MFB_META	std_logic_vector(PCIE_UP_MFB_REGIONS*PCIE_RQ_META_WIDTH - 1 downto 0)	out
PCIE_UP_MFB_SOF	std_logic_vector(PCIE_UP_MFB_REGIONS - 1 downto 0)	out
PCIE_UP_MFB_EOF	std_logic_vector(PCIE_UP_MFB_REGIONS - 1 downto 0)	out
PCIE_UP_MFB_SOF_POS	std_logic_vector(PCIE_UP_MFB_REGIONS*max(1, log2(PCIE_UP_MFB_REGION_SIZE))-1 downto 0)	out
PCIE_UP_MFB_EOF_POS	std_logic_vector(PCIE_UP_MFB_REGIONS*max(1, log2(PCIE_UP_MFB_REGION_SIZE*PCIE_UP_MFB_BLOCK_SIZE))-1 downto 0)	out
PCIE_UP_MFB_SRC_RDY	std_logic	out
PCIE_UP_MFB_DST_RDY	std_logic	in

Subcomponents

Subcomponents

• Input Buffer
• Transaction Buffer
• Header Insertor
• Header Manager
• Software Manager

UVM Verification

Verification Plan

TODO:

Coverage Mesure

There is three test in Multiver script. High percentage of uncovered lines is due to unreacheable states and due to mi comunication with software manager. Mi comunication is tested by hw tests.

test configuration

conf name	Regions	Max packet size	buffer addres width	input fifo (RX)	channels num
default	1(~40Gb/s)	2^16-1	16-bit	NONE	2
32_channel	1(~40Gb/s)	2^16-1	16-bit	NONE	32
32_channel	1(~40Gb/s)	2^16-1	16-bit	On input	2

coverage

conf name	base	full speed	merge
default	63.1942%	63.4521%	64.0038%
32_channels	62.6153%	61.4392%	62.7494%
opt_fifo_en	65.3934%	64.9822%	65.9905%

Delay is mesure only for full spead test. Which allweys accept output from DUT. Delay represents how many nanoseconds take to go through DMA Calypte.

delay

conf name	min	max	average	standard deviation
default	53ns	68ns	57ns	5ns
32_channels	40ns	1752ns	56ns	63ns
opt_fifo_en	44ns	428ns	294ns	158ns