PCIE CONVERSION UNITS

ENTITY PCIE_CQ_AXI2MFB IS

The Purpose of this component is to convert AXI to MFB bus. Supported are 512b and 256b with and without straddling, but variants with straddling and all 256 variant has not been tested.

Generics

Generic	Type	Default	Description
=====	MFB BUS CONFIGURATION:	=====	Supported configurations are: (2,1,8,32), (1,1,8,32)
MFB_REGIONS	natural	2
MFB_REGION_SIZE	natural	1
MFB_BLOCK_SIZE	natural	8
MFB_ITEM_WIDTH	natural	32
MFB_REGION_WIDTH	natural	MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH	MFB bus: width of single data region in bits, auxiliary parameter, do not change value!
=====	AXI BUS CONFIGURATION:	=====	CQ_USER_WIDTH = 183 for Gen3x16 PCIe - with straddling and without straddling! CQ_USER_WIDTH = 88 for Gen3x8 PCIe - without straddling! CQ_USER_WIDTH = 85 for Gen3x8 PCIe - without straddling!
AXI_CQUSER_WIDTH	natural	183
AXI_DATA_WIDTH	natural	MFB_REGIONS*MFB_REGION_WIDTH
STRADDLING	boolean	false	Straddling is permited only for CQ_USER_WIDTH = 183
DEVICE	string	“ULTRASCALE”	Select correct FPGA device: “ULTRASCALE”, “VIRTEX7”

Ports

Port	Type	Mode	Description
=====	AXI Completer Request Interface (CQ) - Xilinx FPGA Only	=====	See Xilinx PG213 (UltraScale+ Devices Integrated Block for PCI Express).
CQ_AXI_DATA	std_logic_vector(AXI_DATA_WIDTH-1 downto 0)	in	CQ_AXI: Data word. For detailed specifications, see Xilinx PG213.
CQ_AXI_USER	std_logic_vector(AXI_CQUSER_WIDTH-1 downto 0)	in	CQ_AXI: Set of signals with sideband information about trasferred transaction. For detailed specifications, see Xilinx PG213.
CQ_AXI_LAST	std_logic	in	CQ_AXI: Indication of the last word of a transaction. For detailed specifications, see Xilinx PG213.
CQ_AXI_KEEP	std_logic_vector(AXI_DATA_WIDTH/32-1 downto 0)	in	CQ_AXI: Indication of valid data: each bit determines validity of different Dword. For detailed specifications, see Xilinx PG213.
CQ_AXI_VALID	std_logic	in	CQ_AXI: Indication of valid data: i.e. completer is ready to send a transaction. For detailed specifications, see Xilinx PG213.
CQ_AXI_READY	std_logic	out	CQ_AXI: User application is ready to receive a transaction. For detailed specifications, see Xilinx PG213.
=====	MFB Completer Request Interface (CQ) - Intel FPGA Only	=====	=====
CQ_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REGION_WIDTH-1 downto 0)	out	CQ_MFB: data word with frames (packets)
CQ_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out	CQ_MFB: Start Of Frame (SOF) flag for each MFB region
CQ_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out	CQ_MFB: End Of Frame (EOF) flag for each MFB region
CQ_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)	out	CQ_MFB: SOF position for each MFB region in MFB blocks
CQ_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	out	CQ_MFB: EOF position for each MFB region in MFB items
CQ_MFB_SRC_RDY	std_logic	out	CQ_MFB: source ready of each MFB bus
CQ_MFB_DST_RDY	std_logic	in	CQ_MFB: destination ready of each MFB bus
=====	CQ_AXI_USER SIGNAL ITEMS	=====	Ports below are valid only with CQ_MFB_SOF
CQ_TPH_PRESENT	std_logic_vector(MFB_REGIONS-1 downto 0)	out	This bit indicates presence of Transaction Processing Hint (TPH)
CQ_TPH_TYPE	std_logic_vector(MFB_REGIONS*2-1 downto 0)	out	These two bits provide the value of the PH field associated with the hint
CQ_TPH_ST_TAG	std_logic_vector(MFB_REGIONS*8-1 downto 0)	out	This output provides the 8-bit Steering Tag associated with the hint
CQ_FBE	std_logic_vector(MFB_REGIONS*4-1 downto 0)	out	Byte enables for the first DWORD
CQ_LBE	std_logic_vector(MFB_REGIONS*4-1 downto 0)	out	Byte enables for the last DWORD

ENTITY PCIE_CC_MFB2AXI IS

The Purpose of this component is to convert MFB to AXI bus. Supported is only 512b variant without straddling

Generics

Generic	Type	Default	Description
=====	MFB BUS CONFIGURATION:	=====	Supported configuration is: (2,1,8,32), (1,1,8,32)
MFB_REGIONS	natural	2
MFB_REGION_SIZE	natural	1
MFB_BLOCK_SIZE	natural	8
MFB_ITEM_WIDTH	natural	32
MFB_REGION_WIDTH	natural	MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH	MFB bus: width of single data region in bits, auxiliary parameter, do not change value!
=====	AXI BUS CONFIGURATION:	=====	CC_USER_WIDTH = 81 for Gen3x16 PCIe - without straddling! CC_USER_WIDTH = 33 for Gen3x8 PCIe - without straddling!
AXI_CCUSER_WIDTH	natural	81
AXI_DATA_WIDTH	natural	512
STRADDLING	boolean	false	Not supported

Ports

Port	Type	Mode	Description
=====	MFB Completer Request Interface (CC) - Intel FPGA Only	=====	=====
CC_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REGION_WIDTH-1 downto 0)	in	CC_MFB: data word with frames (packets)
CC_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in	CC_MFB: Start Of Frame (SOF) flag for each MFB region
CC_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in	CC_MFB: End Of Frame (EOF) flag for each MFB region
CC_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)	in	CC_MFB: SOF position for each MFB region in MFB blocks
CC_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	in	CC_MFB: EOF position for each MFB region in MFB items
CC_MFB_SRC_RDY	std_logic	in	CC_MFB: source ready of each MFB bus
CC_MFB_DST_RDY	std_logic	out	CC_MFB: destination ready of each MFB bus
=====	AXI Completer Request Interface (CC) - Xilinx FPGA Only	=====	See Xilinx PG213 (UltraScale+ Devices Integrated Block for PCI Express).
CC_AXI_DATA	std_logic_vector(AXI_DATA_WIDTH-1 downto 0)	out	CC_AXI: Data word. For detailed specifications, see Xilinx PG213.
CC_AXI_USER	std_logic_vector(AXI_CCUSER_WIDTH-1 downto 0)	out	CC_AXI: Set of signals with sideband information about trasferred transaction. For detailed specifications, see Xilinx PG213.
CC_AXI_LAST	std_logic	out	CC_AXI: Indication of the last word of a transaction. For detailed specifications, see Xilinx PG213.
CC_AXI_KEEP	std_logic_vector(AXI_DATA_WIDTH/32-1 downto 0)	out	CC_AXI: Indication of valid data: each bit determines validity of different Dword. For detailed specifications, see Xilinx PG213.
CC_AXI_VALID	std_logic	out	CC_AXI: Indication of valid data: i.e. completer is ready to send a transaction. For detailed specifications, see Xilinx PG213.
CC_AXI_READY	std_logic	in	CC_AXI: User application is ready to receive a transaction. For detailed specifications, see Xilinx PG213.