Simple dual-port BRAM
- ENTITY SDP_BRAM IS
- Generics
PortsGeneric
Type
Default
Description
DATA_WIDTH
integer
64
Data word width in bits. If BLOCK_ENABLE is True then DATA_WIDTH must be N*BLOCK_WIDTH.
ITEMS
integer
512
Depth of BRAM in number of the data words.
BLOCK_ENABLE
boolean
False
Enable masking of WR_DATA signal per BLOCK_WIDTH.
BLOCK_WIDTH
natural
8
Width of one data block. Allowed values are 8 or 9. The parameter is ignored when BLOCK_ENABLE=False.
COMMON_CLOCK
boolean
True
Designate whether read port and write port are clocked with a common clock or with independent clocks. Possible values:
True = clock write port and read port with WR_CLK
False = clock write port with WR_CLK and read port with RD_CLK
OUTPUT_REG
boolean
True
Output directly from BRAM or throw register (better timing).
METADATA_WIDTH
integer
0
Width of read metadata signal
DEVICE
string
“ULTRASCALE”
The DEVICE parameter allows the correct selection of the RAM implementation according to the FPGA used. Supported values are:
“7SERIES”
“ULTRASCALE”
“STRATIX10”
“ARRIA10”
“AGILEX”
Port
Type
Mode
Description
=====
WRITE PORT
=====
=====
WR_CLK
std_logic
in
Clock signal for write port. Also clock signal for read port when parameter COMMON_CLOCK = True.
WR_RST
std_logic
in
Reset signal synchronous with WR_CLK. Used only when parameter COMMON_CLOCK = True for resetting valid bit of read data.
WR_EN
std_logic
in
Enable of write port.
WR_BE
std_logic_vector(max((DATA_WIDTH/BLOCK_WIDTH),1)-1 downto 0)
in
Block enable of written data, used only when BLOCK_ENABLE = True.
WR_ADDR
std_logic_vector(log2(ITEMS)-1 downto 0)
in
Write address.
WR_DATA
std_logic_vector(DATA_WIDTH-1 downto 0)
in
Write data input.
=====
READ PORT
=====
=====
RD_CLK
std_logic
in
Clock signal for read port when parameter COMMON_CLOCK = False. Unused when COMMON_CLOCK = True.
RD_RST
std_logic
in
Reset signal synchronous with RD_CLK. Used only when parameter COMMON_CLOCK = False for resetting valid bit of read data.
RD_EN
std_logic
in
Read enable signal, it is only used to generate RD_DATA_VLD.
RD_PIPE_EN
std_logic
in
Clock enable of read port.
RD_META_IN
std_logic_vector(METADATA_WIDTH-1 downto 0)
in
Metadata propagated when RD_PIPE_EN==’1’ (valid on RD_EN)
RD_ADDR
std_logic_vector(log2(ITEMS)-1 downto 0)
in
Read address.
RD_DATA
std_logic_vector(DATA_WIDTH-1 downto 0)
out
Read data output.
RD_META_OUT
std_logic_vector(METADATA_WIDTH-1 downto 0)
out
Metadata propagated when RD_PIPE_EN==’1’ (valid on RD_DATA_VLD)
RD_DATA_VLD
std_logic
out
Valid bit of output read data.
Simple dual-port BRAM with Byte Enable
- ENTITY SDP_BRAM_BE IS
A wrapper for SDP_BRAM to abstract Block Enable signal. (Byte Enable with arbitrary width.)
Generics
PortsGeneric
Type
Default
Description
BLOCK_ENABLE
boolean
False
Use Block Enable
BLOCK_WIDTH
integer
8
Width of Block enabled by signal WR_BE Use multiples of 8 or 9 for highest effectivness
=====
Other SDP_BRAM generics
=====
See entity of SDP_BRAM for more detail
DATA_WIDTH
integer
64
ITEMS
integer
512
COMMON_CLOCK
boolean
True
OUTPUT_REG
boolean
True
METADATA_WIDTH
integer
0
DEVICE
string
“ULTRASCALE”
Port
Type
Mode
Description
=====
SDP_BRAM ports
=====
See entity of SDP_BRAM for more detail
WR_CLK
std_logic
in
WR_RST
std_logic
in
WR_EN
std_logic
in
WR_BE
std_logic_vector(DATA_WIDTH/BLOCK_WIDTH-1 downto 0)
in
WR_ADDR
std_logic_vector(log2(ITEMS)-1 downto 0)
in
WR_DATA
std_logic_vector(DATA_WIDTH-1 downto 0)
in
RD_CLK
std_logic
in
RD_RST
std_logic
in
RD_EN
std_logic
in
RD_PIPE_EN
std_logic
in
RD_META_IN
std_logic_vector(METADATA_WIDTH-1 downto 0)
in
RD_ADDR
std_logic_vector(log2(ITEMS)-1 downto 0)
in
RD_DATA
std_logic_vector(DATA_WIDTH-1 downto 0)
out
RD_META_OUT
std_logic_vector(METADATA_WIDTH-1 downto 0)
out
RD_DATA_VLD
std_logic
out