MFB Switch Simple
- ENTITY MFB_SWITCH_SIMPLE IS
The MFB_SWITCH_SIMPLE component sends each packet from one of the RX inputs to the TX output that RX_MFB_SEL selects. Each TX output has one MFB_MERGER_SIMPLE_GEN with an input FIFO for each RX input. The merger starts a packet only when the EOF of this packet is already in the FIFO. So a started packet never waits for an RX input that waits for another TX output. PKT_SIZE_MAX sets the size of the longest packet. Each FIFO must hold this packet.
Generics
PortsGeneric
Type
Default
Description
PORTS
natural
2
REGIONS
natural
4
REGION_SIZE
natural
8
BLOCK_SIZE
natural
8
ITEM_WIDTH
natural
8
META_WIDTH
natural
1
FIFO_DEPTH
natural
512
Depth of the FIFO for each pair of an RX input and a TX output in words.
PKT_SIZE_MAX
natural
2**14
Maximum size of a packet in MFB items.
MASKING_EN
boolean
True
Enable masking SOF and EOF due to switch to the other input. The switch requires True.
CNT_MAX
integer
64
Maximum amount of clock periods with destination ready before it tries to switch to the other input.
DEVICE
string
“AGILEX”
FPGA device name: ULTRASCALE, STRATIX10, AGILEX, …
Port
Type
Mode
Description
=====
Clock and Reset
=====
=====
CLK
std_logic
in
RESET
std_logic
in
=====
Multiple input MFB interfaces
=====
=====
RX_MFB_SEL
slv_array_t(PORTS-1 downto 0)(REGIONS*max(1,log2(PORTS))-1 downto 0)
in
valid with SOF
RX_MFB_META
slv_array_t(PORTS-1 downto 0)(REGIONS*META_WIDTH-1 downto 0)
in
RX_MFB_DATA
slv_array_t(PORTS-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)
in
RX_MFB_SOF
slv_array_t(PORTS-1 downto 0)(REGIONS-1 downto 0)
in
RX_MFB_EOF
slv_array_t(PORTS-1 downto 0)(REGIONS-1 downto 0)
in
RX_MFB_SOF_POS
slv_array_t(PORTS-1 downto 0)(REGIONS*max(1, log2(REGION_SIZE))-1 downto 0)
in
RX_MFB_EOF_POS
slv_array_t(PORTS-1 downto 0)(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0)
in
RX_MFB_SRC_RDY
std_logic_vector(PORTS-1 downto 0)
in
RX_MFB_DST_RDY
std_logic_vector(PORTS-1 downto 0)
out
=====
Multiple output MFB interfaces
=====
=====
TX_MFB_META
slv_array_t(PORTS-1 downto 0)(REGIONS*META_WIDTH-1 downto 0)
out
TX_MFB_DATA
slv_array_t(PORTS-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)
out
TX_MFB_SOF
slv_array_t(PORTS-1 downto 0)(REGIONS-1 downto 0)
out
TX_MFB_EOF
slv_array_t(PORTS-1 downto 0)(REGIONS-1 downto 0)
out
TX_MFB_SOF_POS
slv_array_t(PORTS-1 downto 0)(REGIONS*max(1, log2(REGION_SIZE))-1 downto 0)
out
TX_MFB_EOF_POS
slv_array_t(PORTS-1 downto 0)(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0)
out
TX_MFB_SRC_RDY
std_logic_vector(PORTS-1 downto 0)
out
TX_MFB_DST_RDY
std_logic_vector(PORTS-1 downto 0)
in