MFB Merger

ENTITY MFB_MERGER IS

Merges two input MVB+MFB interfaces in one output interface Contains input FIFOs and output PIPEs.

Generics

Generic	Type	Default	Description
=====	TX MVB characteristics	=====	=====
MVB_ITEMS	integer	2	number of headers
=====	TX MFB characteristics	=====	=====
MFB_REGIONS	integer	2	number of regions in word
MFB_REG_SIZE	integer	1	number of blocks in region
MFB_BLOCK_SIZE	integer	8	number of items in block
MFB_ITEM_WIDTH	integer	32	width of one item (in bits)
MFB_META_WIDTH	integer	0	width of MFB metadata
=====	Others	=====	=====
HDR_WIDTH	integer	DMA_DOWNHDR_WIDTH	Width of each MVB item DMA_DOWNHDR_WIDTH, DMA_UPHDR_WIDTH
RX0_PAYLOAD_ENABLED	boolean	true	Data/Payload MFB interface required/active on individual input ports Currently used only in SIMPLE architecture to optimize usage of input/output pipes
RX1_PAYLOAD_ENABLED	boolean	true
IN_MFB_FIFO_EN	boolean	false	To enable optional MFB FIFOs at input
INPUT_FIFO_SIZE	integer	8	Size of input MVB and MFB FIFOs (in words) Minimum value is 2!
SW_TIMEOUT_WIDTH	natural	4	Width of timeout counter, determines the time when the switch to the next active MVB/MFB stream occurs.
IN_PIPE_EN	boolean	false	Input PIPEs enable Only used in architecture SIMPLE. Input registers is created when this is set to false.
OUT_PIPE_EN	boolean	true	Output PIPE enable Only used in architecture SIMPLE. Output register is created when this is set to false.
FIFOX_MULTI_ARCH	string	“SHAKEDOWN”	Architecture of FIFOX_MULTI
DEVICE	string	“ULTRASCALE”	“ULTRASCALE”, “7SERIES”

Ports

Port	Type	Mode	Description
=====	Common interface	=====	=====
CLK	std_logic	in
RESET	std_logic	in
=====	RX interface 0	=====	=====
RX0_MVB_HDR	std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)	in
RX0_MVB_PAYLOAD	std_logic_vector(MVB_ITEMS -1 downto 0)	in	the header is associated with a payload frame on MFB
RX0_MVB_VLD	std_logic_vector(MVB_ITEMS -1 downto 0)	in
RX0_MVB_SRC_RDY	std_logic	in
RX0_MVB_DST_RDY	std_logic	out
RX0_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	in
RX0_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	in	Allways valid, metadata merged by words
RX0_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX0_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX0_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	in
RX0_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	in
RX0_MFB_SRC_RDY	std_logic	in
RX0_MFB_DST_RDY	std_logic	out
=====	RX interface 1	=====	=====
RX1_MVB_HDR	std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)	in
RX1_MVB_PAYLOAD	std_logic_vector(MVB_ITEMS -1 downto 0)	in	the header is associated with a payload frame on MFB
RX1_MVB_VLD	std_logic_vector(MVB_ITEMS -1 downto 0)	in
RX1_MVB_SRC_RDY	std_logic	in
RX1_MVB_DST_RDY	std_logic	out
RX1_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	in
RX1_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	in	Allways valid, metadata merged by words
RX1_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX1_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX1_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	in
RX1_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	in
RX1_MFB_SRC_RDY	std_logic	in
RX1_MFB_DST_RDY	std_logic	out
=====	TX interface	=====	=====
TX_MVB_HDR	std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)	out
TX_MVB_PAYLOAD	std_logic_vector(MVB_ITEMS -1 downto 0)	out	the header is associated with a payload frame on MFB
TX_MVB_VLD	std_logic_vector(MVB_ITEMS -1 downto 0)	out
TX_MVB_SRC_RDY	std_logic	out
TX_MVB_DST_RDY	std_logic	in
TX_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	out
TX_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	out	Allways valid, metadata merged by words
TX_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	out
TX_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	out
TX_MFB_SRC_RDY	std_logic	out
TX_MFB_DST_RDY	std_logic	in

There are three variants of MFB Merger:

1. MFB Merger Full

   Merges two input MVB+MFB interfaces in one output interface. Only contains 1 input register for each input interface and 1 output register. Has lower throughput compared to the OLD MFB Merger architecture, but much lesser resource consumption. This is the preffered architecture for this unit!

2. MFB Merger Gen

   MFB+MVB bus merger with generic number of inputs

3. MFB Merger Old

   Merges two input MVB+MFB interfaces in one output interface Contains input FIFOs and output PIPEs. This architecture has not been verified, as it is not supposed to be used. Use architecture FULL instead!