MFB Merger Gen
- ENTITY MFB_MERGER_GEN IS
MFB+MVB bus merger with generic number of inputs.
This module merges multiple input MVB+MFB streams into a single output stream using a binary tree of 2:1 MFB_MERGER units. The number of inputs can be any positive integer (non-power-of-2 inputs are padded internally).
MVB and MFB Interface Usage
The MVB interface carries header information (e.g., DMA descriptors) while the MFB interface carries the associated data payload. Each MVB header can be marked as having an associated payload frame using the
RX_MVB_PAYLOADsignal. WhenRX_MVB_PAYLOAD(i)(j) = '1', the j-th header on input i is associated with data on the MFB interface. The merger maintains this association throughout the merging process.Warning
Related MVB headers and their corresponding MFB data frames must arrive at each input in the same order they are expected to appear on the output. The merger pairs headers with payloads based on arrival order, not by content matching. Out-of-order arrival will result in incorrect header-payload pairing.
RX_MVB_PAYLOAD Signal Usage
This signal indicates which MVB headers have associated data payload on MFB.
When
'1': The corresponding header has an associated data frame on MFBWhen
'0': The header is standalone (control-only, no data payload)
Each bit in
RX_MVB_PAYLOAD(i)corresponds to one MVB header item on input i.RX_PAYLOAD_EN Generic
Controls whether the MFB data path is implemented for each input port.
When
true: Full MVB+MFB merging with header-payload associationWhen
false: Only MVB headers are processed; MFB path is bypassed
Use
falsefor inputs that only send control headers without data payload, reducing resource consumption by eliminating unnecessary MFB pipeline stages.Features
Configurable number of input streams (any positive integer)
Configurable MVB item count and MFB geometry
Optional mid-stage MFB FIFOs for buffering
Configurable input/output pipelining
Timeout-based stream switching
Metadata support on MFB interface
PortsGeneric
Type
Default
Description
=====
GENERAL PARAMETERS
=====
=====
MERGER_INPUTS
integer
2
Number of merger input streams Can be any positive integer (non-power-of-2 values are padded internally)
=====
MVB INTERFACE PARAMETERS
=====
=====
MVB_ITEMS
integer
2
Number of MVB header items (parallel headers per cycle)
MVB_ITEM_WIDTH
integer
32
Width of each MVB header item in bits
=====
MFB INTERFACE PARAMETERS
=====
=====
MFB_REGIONS
integer
2
Number of MFB regions per word
MFB_REG_SIZE
integer
1
Number of blocks per region
MFB_BLOCK_SIZE
integer
8
Number of items per block
MFB_ITEM_WIDTH
integer
32
Width of one MFB item in bits
MFB_META_WIDTH
integer
1
Width of MFB metadata bus in bits
=====
GENERAL PARAMETERS
=====
=====
INPUT_FIFO_SIZE
integer
8
Depth of input MVB and MFB FIFOs in words Minimum value is 2
RX_PAYLOAD_EN
b_array_t(MERGER_INPUTS-1 downto 0)
(others => true)
MFB data payload enable for each input port RX_PAYLOAD_EN(i) = true: Full MVB+MFB operation on input i RX_PAYLOAD_EN(i) = false: MVB headers only on input i (MFB path optimized away) Use false for inputs that only carry control headers without data
SW_TIMEOUT_WIDTH
natural
4
Width of stream switch timeout counter Timeout = 2^SW_TIMEOUT_WIDTH cycles of inactivity before switching Higher values reduce switching frequency but increase latency for the non-active stream. Lower values may create gaps between MFB packets during switching, reducing throughput (only one input port is read per cycle per merger stage)
MID_MFB_FIFOS_EN
boolean
False
Enable optional MFB FIFOs at intermediate merger stages false: No FIFOs between merger stages (input FIFOs only) true: Adds MFB_FIFOX buffers at each internal tree stage
IN_PIPE_EN
boolean
false
Enable input PIPE stages for all internal 2:1 merger units true: Uses MVB_PIPE and MFB_PIPE components for registered inputs false: Uses simple registers (combinatorial input path)
OUT_PIPE_EN
boolean
true
Enable output PIPE stage for all internal 2:1 merger units true: Uses MVB_PIPE and MFB_PIPE components for registered outputs false: Uses simple output registers
FIFOX_MULTI_ARCH
string
“SHAKEDOWN”
Architecture selection for internal FIFOX_MULTI component Supported values: * “SHAKEDOWN”: Handshake-based FIFO with better buffering and throughput * “FULL”: Standard implementation with wide MUXes
DEVICE
string
“ULTRASCALE”
Target device family for FIFO/PIPE implementation Specifies the FPGA device family for optimal resource inference
Port
Type
Mode
Description
=====
COMMON SIGNALS
=====
=====
CLK
std_logic
in
System clock
RESET
std_logic
in
Synchronous reset (active high)
=====
RX INTERFACES (per input port)
=====
=====
RX_MVB_DATA
slv_array_t (MERGER_INPUTS-1 downto 0)(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
in
MVB header bus array (one per input port) RX_MVB_DATA(i) contains MVB_ITEMS headers, each MVB_ITEM_WIDTH bits
RX_MVB_PAYLOAD
slv_array_t (MERGER_INPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)
in
Payload association flags array (one per input port) RX_MVB_PAYLOAD(i)(j) = ‘1’: Header j on input i has associated MFB data
RX_MVB_VLD
slv_array_t (MERGER_INPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)
in
Header valid flags array (one per input port)
RX_MVB_SRC_RDY
std_logic_vector(MERGER_INPUTS-1 downto 0)
in
Source ready array (one per input port) Backpressure from merger to upstream sender
RX_MVB_DST_RDY
std_logic_vector(MERGER_INPUTS-1 downto 0)
out
Destination ready array (one per input port) Flow control from merger to upstream sender
RX_MFB_DATA
slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
MFB data bus array (one per input port) Organized as: MFB_REGIONS x MFB_REG_SIZE x MFB_BLOCK_SIZE x MFB_ITEM_WIDTH bits
RX_MFB_META
slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
in
MFB metadata bus array (one per input port) Always valid when MFB data is valid; passed through unchanged
RX_MFB_SOF
slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)
in
Start of Frame flags array (one per input port) RX_MFB_SOF(i)(r) = ‘1’: Region r on input i contains SOF
RX_MFB_EOF
slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)
in
End of Frame flags array (one per input port) RX_MFB_EOF(i)(r) = ‘1’: Region r on input i contains EOF
RX_MFB_SOF_POS
slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
in
SOF position array (one per input port) Indicates which block within the region contains the SOF
RX_MFB_EOF_POS
slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
EOF position array (one per input port) Indicates which item within the block contains the EOF
RX_MFB_SRC_RDY
std_logic_vector(MERGER_INPUTS-1 downto 0)
in
Source ready array (one per input port)
RX_MFB_DST_RDY
std_logic_vector(MERGER_INPUTS-1 downto 0)
out
Destination ready array (one per input port)
=====
TX INTERFACE (merged output)
=====
=====
TX_MVB_DATA
std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
out
Merged MVB header bus Contains headers from all inputs, merged based on activity
TX_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
Payload association flags for merged output Maintains the header-to-payload relationship from input streams
TX_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
Header valid flags for merged output
TX_MVB_SRC_RDY
std_logic
out
Source ready - backpressure from downstream receiver Asserted when the merger has valid data to send
TX_MVB_DST_RDY
std_logic
in
Destination ready - flow control from downstream consumer When ‘1’, the consumer can accept new data
TX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
Merged MFB data bus Contains payload data from all inputs, synchronized with TX_MVB_DATA
TX_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
out
Merged MFB metadata bus Metadata from active input stream passed through unchanged
TX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
Start of Frame flags for merged output
TX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
End of Frame flags for merged output
TX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
out
SOF position for merged output
TX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
EOF position for merged output
TX_MFB_SRC_RDY
std_logic
out
Source ready - backpressure from downstream receiver Asserted when the merger has valid MFB data to send
TX_MFB_DST_RDY
std_logic
in
Destination ready - flow control from downstream consumer
MFB Merger
- ENTITY MFB_MERGER IS
Merges two input MVB+MFB interfaces into a single output interface.
The module alternates between two input streams (RX0 and RX1) and merges them into one output stream (TX). It handles both MVB (control headers) and MFB (data payload) interfaces simultaneously, maintaining association between headers and their corresponding data frames.
MVB and MFB Interface Usage
The MVB interface carries header information (e.g., DMA descriptors) while the MFB interface carries the associated data payload. Each MVB header can be marked as having an associated payload frame using the
RXx_MVB_PAYLOADsignal. WhenRXx_MVB_PAYLOAD(i) = '1', the i-th header is associated with data on the MFB interface. The merger maintains this association throughout the merging process, ensuring headers and their payloads emerge together on the TX interface.Warning
Related MVB headers and their corresponding MFB data frames must arrive at the input in the same order they are expected to appear on the output. The merger pairs headers with payloads based on arrival order, not by content matching. If a header with
RXx_MVB_PAYLOAD(i)='1'arrives, the next MFB frame on that input port will be associated with that header. Out-of-order arrival will result in incorrect header-payload pairing.RXx_MVB_PAYLOAD Signal Usage
This signal indicates which MVB headers have associated data payload on MFB.
When
'1': The corresponding header has an associated data frame on MFBWhen
'0': The header is standalone (control-only, no data payload)
Each bit in
RXx_MVB_PAYLOADcorresponds to one MVB header item.RXx_PAYLOAD_ENABLED Generic
Controls whether the MFB data path is implemented for each input port.
When
true: Full MVB+MFB merging with header-payload associationWhen
false: Only MVB headers are processed; MFB path is bypassed
Use
falsewhen an input port only sends control headers without data payload, reducing resource consumption by eliminating unnecessary MFB pipeline stages.Features
Configurable MVB item count and MFB geometry
Optional input FIFOs for MFB interface
Configurable input/output pipelining
Timeout-based stream switching
Metadata support on MFB interface
PortsGeneric
Type
Default
Description
=====
MVB INTERFACE PARAMETERS
=====
=====
MVB_ITEMS
integer
2
Number of MVB header items (parallel headers per cycle) Determines the width of MVB-related signals: MVB_ITEMS * HDR_WIDTH
=====
MFB INTERFACE PARAMETERS
=====
=====
MFB_REGIONS
integer
2
Number of MFB regions per word Each region can independently carry SOF/EOF markers
MFB_REG_SIZE
integer
1
Number of blocks per region Affects EOF position width: log2(MFB_REG_SIZE * MFB_BLOCK_SIZE)
MFB_BLOCK_SIZE
integer
8
Number of items per block Combined with ITEM_WIDTH determines total MFB data width
MFB_ITEM_WIDTH
integer
32
Width of one MFB item in bits Typical values: 32, 64, 128, 256
MFB_META_WIDTH
integer
0
Width of MFB metadata bus in bits Set to 0 to disable metadata support Metadata is passed through unchanged for each region
=====
GENERAL PARAMETERS
=====
=====
HDR_WIDTH
integer
DMA_DOWNHDR_WIDTH
Width of each MVB header item in bits Common values: DMA_DOWNHDR_WIDTH (downstream) or DMA_UPHDR_WIDTH (upstream) from dma_bus_pack package
RX0_PAYLOAD_ENABLED
boolean
true
Enable MFB data payload processing on RX0 input port true: Full MVB+MFB operation with header-payload association false: MVB headers processed; MFB path optimized away (FAKE_PIPE) Use false when RX0 only carries standalone headers without data
RX1_PAYLOAD_ENABLED
boolean
true
Enable MFB data payload processing on RX1 input port Same behavior as RX0_PAYLOAD_ENABLED but for the second input
IN_MFB_FIFO_EN
boolean
false
Enable optional MFB FIFOs at input ports for additional buffering true: Instantiates MFB_FIFOX buffers of INPUT_FIFO_SIZE depth false: Direct connection without input buffering
INPUT_FIFO_SIZE
integer
8
Depth of input MVB and MFB FIFOs in words Minimum value is 2 Only used when IN_MFB_FIFO_EN = true
SW_TIMEOUT_WIDTH
natural
4
Width of stream switch timeout counter Timeout = 2^SW_TIMEOUT_WIDTH cycles of inactivity before switching Higher values reduce switching frequency but increase latency for the non-active stream. Lower values may create bigger gaps between MFB packets during switching, reducing throughput (only one input port is read per cycle)
IN_PIPE_EN
boolean
false
Enable input PIPE stages for registered inputs true: Uses MVB_PIPE and MFB_PIPE components for registered inputs false: Uses simple registers (combinatorial input path)
OUT_PIPE_EN
boolean
true
Enable output PIPE stage for registered outputs true: Uses MVB_PIPE and MFB_PIPE components for registered outputs false: Uses simple output registers
FIFOX_MULTI_ARCH
string
“SHAKEDOWN”
Architecture selection for internal FIFOX_MULTI component Supported values: * “SHAKEDOWN”: Handshake-based FIFO with better buffering and throughput * “FULL”: Standard implementation with wide MUXes
DEVICE
string
“ULTRASCALE”
Target device family for FIFO/PIPE implementation Specifies the FPGA device family for optimal resource inference
Port
Type
Mode
Description
=====
COMMON SIGNALS
=====
=====
CLK
std_logic
in
System clock
RESET
std_logic
in
Synchronous reset (active high)
=====
RX INTERFACE 0 (MVB)
=====
=====
RX0_MVB_HDR
std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)
in
MVB header bus containing up to MVB_ITEMS headers in parallel Each header is HDR_WIDTH bits wide Format: {header[MVB_ITEMS-1], …, header[0]}
RX0_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS -1 downto 0)
in
Payload association flags for each MVB header item Bit i = ‘1’: Header i has associated data payload on MFB interface Bit i = ‘0’: Header i is standalone (control-only, no MFB data) This signal establishes the header-to-payload relationship that the merger maintains throughout the merging process
RX0_MVB_VLD
std_logic_vector(MVB_ITEMS -1 downto 0)
in
Header valid flags Bit i = ‘1’: Header i (and payload if RX0_MVB_PAYLOAD(i)=’1’) is valid
RX0_MVB_SRC_RDY
std_logic
in
Source ready - backpressure signal from downstream receiver When ‘0’, the receiver cannot accept data; hold all signals stable
RX0_MVB_DST_RDY
std_logic
out
Destination ready - flow control to upstream sender When ‘1’, the merger can accept a new header/payload combination
=====
RX INTERFACE 0 (MFB)
=====
=====
RX0_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
MFB data bus carrying payload data Organized as: MFB_REGIONS regions x MFB_REG_SIZE blocks x MFB_BLOCK_SIZE items x MFB_ITEM_WIDTH bits Total width: MFB_REGIONS * MFB_REG_SIZE * MFB_BLOCK_SIZE * MFB_ITEM_WIDTH bits
RX0_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
in
MFB metadata bus (optional) One metadata word per region, each MFB_META_WIDTH bits wide Always valid when MFB data is valid; passed through unchanged Tied to ‘0’ by default when MFB_META_WIDTH = 0
RX0_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
Start of Frame flags - one per region RX0_MFB_SOF(i) = ‘1’: Region i contains the start of a new packet
RX0_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
End of Frame flags - one per region RX0_MFB_EOF(i) = ‘1’: Region i contains the end of a packet
RX0_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
in
SOF position within each region Indicates which block within the region contains the SOF Width: MFB_REGIONS * log2(MFB_REG_SIZE) bits
RX0_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
EOF position within each block Indicates which item within the block contains the EOF Width: MFB_REGIONS * log2(MFB_REG_SIZE * MFB_BLOCK_SIZE) bits
RX0_MFB_SRC_RDY
std_logic
in
Source ready - backpressure signal from downstream receiver
RX0_MFB_DST_RDY
std_logic
out
Destination ready - flow control to upstream sender
=====
RX INTERFACE 1 (MVB)
=====
=====
RX1_MVB_HDR
std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)
in
MVB header bus (same format as RX0_MVB_HDR)
RX1_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS -1 downto 0)
in
Payload association flags (same format as RX0_MVB_PAYLOAD)
RX1_MVB_VLD
std_logic_vector(MVB_ITEMS -1 downto 0)
in
Header valid flags (same format as RX0_MVB_VLD)
RX1_MVB_SRC_RDY
std_logic
in
Source ready (same format as RX0_MVB_SRC_RDY)
RX1_MVB_DST_RDY
std_logic
out
Destination ready (same format as RX0_MVB_DST_RDY)
=====
RX INTERFACE 1 (MFB)
=====
=====
RX1_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
MFB data bus (same format as RX0_MFB_DATA)
RX1_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
in
MFB metadata bus (same format as RX0_MFB_META)
RX1_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
Start of Frame flags (same format as RX0_MFB_SOF)
RX1_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
End of Frame flags (same format as RX0_MFB_EOF)
RX1_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
in
SOF position (same format as RX0_MFB_SOF_POS)
RX1_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
EOF position (same format as RX0_MFB_EOF_POS)
RX1_MFB_SRC_RDY
std_logic
in
Source ready (same format as RX0_MFB_SRC_RDY)
RX1_MFB_DST_RDY
std_logic
out
Destination ready (same format as RX0_MFB_DST_RDY)
=====
TX INTERFACE (MVB)
=====
=====
TX_MVB_HDR
std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)
out
Merged MVB header bus Contains headers from both RX0 and RX1, merged based on activity
TX_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS -1 downto 0)
out
Payload association flags for merged output Maintains the header-to-payload relationship from the input streams
TX_MVB_VLD
std_logic_vector(MVB_ITEMS -1 downto 0)
out
Header valid flags for merged output
TX_MVB_SRC_RDY
std_logic
out
Source ready - backpressure from downstream receiver Asserted when the merger has valid data to send
TX_MVB_DST_RDY
std_logic
in
Destination ready - flow control from downstream consumer When ‘1’, the consumer can accept new data
=====
TX INTERFACE (MFB)
=====
=====
TX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
Merged MFB data bus Contains payload data from both RX0 and RX1, synchronized with TX_MVB_HDR
TX_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
out
Merged MFB metadata bus Metadata from active input stream passed through unchanged
TX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
Start of Frame flags for merged output
TX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
End of Frame flags for merged output
TX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
out
SOF position for merged output
TX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
EOF position for merged output
TX_MFB_SRC_RDY
std_logic
out
Source ready - backpressure from downstream receiver Asserted when the merger has valid MFB data to send
TX_MFB_DST_RDY
std_logic
in
Destination ready - flow control from downstream consumer