MFB Merger Gen

ENTITY MFB_MERGER_GEN IS

MFB+MVB bus merger with generic number of inputs.

Merges MERGER_INPUTS input MVB+MFB streams into one output stream. All inputs are arbitrated in one step by a single MFB_MERGER_FLAT unit, whatever their number. This entity adds the optional input FIFOs and the input and output pipes around it. A single input is passed straight through instead.

The MVB interface carries the headers, for example DMA descriptors, and the MFB interface the data payload. RX_MVB_PAYLOAD(i)(j)='1' marks that the j-th header on input i has a frame on MFB. On each input the k-th frame belongs to the k-th header that announces one.

RX_PAYLOAD_EN(i) set to false leaves out the MFB path of input i. Use it for inputs that only send headers, it saves the MFB pipeline stages.

Warning

Headers and frames are paired by order, not by content. On one input the k-th frame on MFB belongs to the k-th header that has RX_MVB_PAYLOAD(i)(j)='1'. A header with '0' takes no frame.

Note

A higher SW_TIMEOUT_WIDTH switches less often, and the other inputs then wait longer. An input waits for up to (MERGER_INPUTS-1) grants, so size the input MFB FIFOs for that wait.

Generics

Generic	Type	Default	Description
=====	GENERAL PARAMETERS	=====	=====
MERGER_INPUTS	integer	2	Number of merger input streams, any positive integer
=====	MVB INTERFACE PARAMETERS	=====	=====
MVB_ITEMS	integer	2	Number of MVB headers per word
MVB_ITEM_WIDTH	integer	32	Width of one MVB header in bits
=====	MFB INTERFACE PARAMETERS	=====	=====
MFB_REGIONS	integer	2	Number of Regions per MFB word
MFB_REG_SIZE	integer	1	Number of Blocks per Region
MFB_BLOCK_SIZE	integer	8	Number of Items per Block
MFB_ITEM_WIDTH	integer	32	Width of one MFB Item in bits
MFB_META_WIDTH	integer	1	Width of MFB metadata in bits
=====	GENERAL PARAMETERS	=====	=====
IN_MFB_FIFO_EN	boolean	false	Enable the input MFB FIFOs. They hold a burst while the output is busy, instead of pushing back on the sources straight away.
INPUT_FIFO_SIZE	integer	8	Obsolete, use IN_MFB_FIFO_SIZE instead, which it sets the default of
IN_MFB_FIFO_SIZE	integer	INPUT_FIFO_SIZE	Depth of the input MFB FIFOs in words, minimum value is 2
IN_MVB_FIFO_EN	boolean	false	Enable the input MVB FIFOs. An input the switch is not serving has its MVB DST_RDY held low. These FIFOs let it keep taking headers.
IN_MVB_FIFO_SIZE	integer	8	Depth of the input MVB FIFOs in words, minimum value is 2
SW_FIFO_ITEMS	natural	MVB_ITEMS*32	Depth of the switch FIFO in items. It holds one item per packet whose header announced a payload.
IN_REG_SKID_EN	boolean	false	Add a skid slot in front of each MFB input register. It shortens the longest path at the cost of one more word of registers per input.
RX_PAYLOAD_EN	b_array_t(MERGER_INPUTS-1 downto 0)	(others => true)	MFB data payload enable for each input port. False leaves out the MFB path of that input.
SW_TIMEOUT_WIDTH	natural	4	Width of the stream switch timeout counter. One input is served for 2**(SW_TIMEOUT_WIDTH-1) MVB words, or until it runs out of headers.
MID_MFB_FIFOS_EN	boolean	False	Obsolete, use IN_MFB_FIFO_EN instead, which it activates
IN_PIPE_EN	boolean	false	Enable the input PIPE stages
OUT_PIPE_EN	boolean	true	Enable the output PIPE stage
FIFOX_MULTI_ARCH	string	“SHAKEDOWN”	Architecture of the internal FIFOX_MULTI, “SHAKEDOWN” or “FULL”
DEVICE	string	“ULTRASCALE”	Target device family

Ports

Port	Type	Mode	Description
=====	COMMON SIGNALS	=====	=====
CLK	std_logic	in
RESET	std_logic	in
=====	RX INTERFACES (per input port)	=====	=====
RX_MVB_DATA	slv_array_t (MERGER_INPUTS-1 downto 0)(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)	in
RX_MVB_PAYLOAD	slv_array_t (MERGER_INPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)	in	Bit j announces that header j on input i has a frame on MFB
RX_MVB_VLD	slv_array_t (MERGER_INPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)	in
RX_MVB_SRC_RDY	std_logic_vector(MERGER_INPUTS-1 downto 0)	in
RX_MVB_DST_RDY	std_logic_vector(MERGER_INPUTS-1 downto 0)	out
RX_MFB_DATA	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	in
RX_MFB_META	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	in	Passed to the output unchanged
RX_MFB_SOF	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)	in
RX_MFB_EOF	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)	in
RX_MFB_SOF_POS	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	in
RX_MFB_EOF_POS	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	in
RX_MFB_SRC_RDY	std_logic_vector(MERGER_INPUTS-1 downto 0)	in
RX_MFB_DST_RDY	std_logic_vector(MERGER_INPUTS-1 downto 0)	out
=====	TX INTERFACE (merged output)	=====	=====
TX_MVB_DATA	std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)	out
TX_MVB_PAYLOAD	std_logic_vector(MVB_ITEMS-1 downto 0)	out	Bit j announces that header j has a frame on MFB
TX_MVB_VLD	std_logic_vector(MVB_ITEMS-1 downto 0)	out
TX_MVB_SRC_RDY	std_logic	out
TX_MVB_DST_RDY	std_logic	in
TX_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	out
TX_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	out	Metadata of the input the word came from, passed through unchanged
TX_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	out
TX_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	out
TX_MFB_SRC_RDY	std_logic	out
TX_MFB_DST_RDY	std_logic	in

MFB Merger Flat

ENTITY MFB_MERGER_FLAT IS

MFB+MVB bus merger which arbitrates all its inputs in a single step.

Merges MERGER_INPUTS input MVB+MFB streams into one output stream.

The MVB interface carries headers and the MFB interface the data payload. RX_MVB_PAYLOAD(i)(j)='1' marks that the j-th header on input i has a frame on MFB. On each input the k-th frame belongs to the k-th header that announces one. Headers and frames must therefore keep the same order.

How it works

Headers and payload are merged by two separate halves. The MVB half is a plain arbiter built on MVB_MERGE_STREAMS. It picks one input and lets its headers out. For every header that announces a payload it also writes the number of that input into the switch FIFO.

The switch FIFO holds one item per packet, in the order the packets leave. The MFB half reads it to learn which input each output word is built from. Every input holds its current word in a register. The packet counts kept beside that register decide how much of the word may leave at once.

Generics

Generic	Type	Default	Description
MERGER_INPUTS	natural	4	Number of merger input streams, must be at least 2
MVB_ITEMS	natural	2	Number of MVB header items (parallel headers per cycle)
MVB_ITEM_WIDTH	natural	32	Width of each MVB header item in bits
MFB_REGIONS	natural	2	Number of Regions per MFB word
MFB_REG_SIZE	natural	1	Number of Blocks per Region
MFB_BLOCK_SIZE	natural	8	Number of Items per Block
MFB_ITEM_WIDTH	natural	32	Width of one MFB Item in bits
MFB_META_WIDTH	natural	1	Width of MFB metadata in bits
IN_REG_SKID_EN	boolean	false	Add a skid slot in front of each MFB input register. It shortens the longest path at the cost of one more word of registers per input.
RX_PAYLOAD_EN	b_array_t(MERGER_INPUTS-1 downto 0)	(others => true)	MFB data payload enable for each input port, false leaves out its MFB path
SW_TIMEOUT_WIDTH	natural	4	Width of the stream switch timeout counter. One input is served for 2**(SW_TIMEOUT_WIDTH-1) MVB words, or until it runs out of headers.
SW_FIFO_ITEMS	natural	MVB_ITEMS*32	Depth of the switch FIFO in items. It holds one item per packet whose header announced a payload.
FIFOX_MULTI_ARCH	string	“SHAKEDOWN”	Architecture of the internal FIFOX_MULTI, “SHAKEDOWN” or “FULL”
DEVICE	string	“ULTRASCALE”	Target device family

Ports

Port	Type	Mode	Description
=====	COMMON SIGNALS	=====	=====
CLK	std_logic	in
RESET	std_logic	in
=====	RX INTERFACES (per input port)	=====	=====
RX_MVB_DATA	slv_array_t (MERGER_INPUTS-1 downto 0)(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)	in
RX_MVB_PAYLOAD	slv_array_t (MERGER_INPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)	in
RX_MVB_VLD	slv_array_t (MERGER_INPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)	in
RX_MVB_SRC_RDY	std_logic_vector(MERGER_INPUTS-1 downto 0)	in
RX_MVB_DST_RDY	std_logic_vector(MERGER_INPUTS-1 downto 0)	out
RX_MFB_DATA	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	in
RX_MFB_META	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	in
RX_MFB_SOF	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)	in
RX_MFB_EOF	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)	in
RX_MFB_SOF_POS	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	in
RX_MFB_EOF_POS	slv_array_t (MERGER_INPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	in
RX_MFB_SRC_RDY	std_logic_vector(MERGER_INPUTS-1 downto 0)	in
RX_MFB_DST_RDY	std_logic_vector(MERGER_INPUTS-1 downto 0)	out
=====	TX INTERFACE (merged output)	=====	=====
TX_MVB_DATA	std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)	out
TX_MVB_PAYLOAD	std_logic_vector(MVB_ITEMS-1 downto 0)	out
TX_MVB_VLD	std_logic_vector(MVB_ITEMS-1 downto 0)	out
TX_MVB_SRC_RDY	std_logic	out
TX_MVB_DST_RDY	std_logic	in
TX_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	out
TX_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	out
TX_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	out
TX_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	out
TX_MFB_SRC_RDY	std_logic	out
TX_MFB_DST_RDY	std_logic	in

MFB Merger

ENTITY MFB_MERGER IS

Merges two MVB+MFB inputs into one output.

Warning

Headers and frames are paired by order, not by content. On one input the k-th frame on MFB belongs to the k-th header that has RXx_MVB_PAYLOAD(i)='1'. A header with '0' takes no frame.

Generics

Generic	Type	Default	Description
=====	MVB INTERFACE PARAMETERS	=====	=====
MVB_ITEMS	integer	2	Number of MVB headers per word
HDR_WIDTH	integer	DMA_DOWNHDR_WIDTH	Width of one MVB header in bits
=====	MFB INTERFACE PARAMETERS	=====	=====
MFB_REGIONS	integer	2	Number of Regions per MFB word
MFB_REG_SIZE	integer	1	Number of Blocks per Region
MFB_BLOCK_SIZE	integer	8	Number of Items per Block
MFB_ITEM_WIDTH	integer	32	Width of one MFB Item in bits
MFB_META_WIDTH	integer	0	Width of MFB metadata in bits, 0 disables it
=====	GENERAL PARAMETERS	=====	=====
RX0_PAYLOAD_ENABLED	boolean	true	MFB data payload enable for the RX0 input port false: MVB headers only, the MFB path is optimized away
RX1_PAYLOAD_ENABLED	boolean	true	MFB data payload enable for the RX1 input port
IN_MFB_FIFO_EN	boolean	false	Enable the input MFB FIFOs
INPUT_FIFO_SIZE	integer	8	Obsolete, use IN_MFB_FIFO_SIZE instead, which it sets the default of
IN_MFB_FIFO_SIZE	integer	INPUT_FIFO_SIZE	Depth of the input MFB FIFOs in words, minimum value is 2
IN_MVB_FIFO_EN	boolean	false	Enable the input MVB FIFOs
IN_MVB_FIFO_SIZE	integer	8	Depth of the input MVB FIFOs in words, minimum value is 2
SW_TIMEOUT_WIDTH	natural	4	Width of the stream switch timeout counter
SW_FIFO_ITEMS	natural	MVB_ITEMS*32	Depth of the switch FIFO in items
IN_PIPE_EN	boolean	false	Enable the input PIPE stages
OUT_PIPE_EN	boolean	true	Enable the output PIPE stage
FIFOX_MULTI_ARCH	string	“SHAKEDOWN”	Architecture of the internal FIFOX_MULTI, “SHAKEDOWN” or “FULL”
DEVICE	string	“ULTRASCALE”	Target device family

Ports

Port	Type	Mode	Description
=====	COMMON SIGNALS	=====	=====
CLK	std_logic	in
RESET	std_logic	in
=====	RX INTERFACE 0	=====	=====
RX0_MVB_HDR	std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)	in
RX0_MVB_PAYLOAD	std_logic_vector(MVB_ITEMS -1 downto 0)	in	Bit i announces that header i has a frame on MFB
RX0_MVB_VLD	std_logic_vector(MVB_ITEMS -1 downto 0)	in
RX0_MVB_SRC_RDY	std_logic	in
RX0_MVB_DST_RDY	std_logic	out
RX0_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	in
RX0_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	in	Passed to the output unchanged
RX0_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX0_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX0_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	in
RX0_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	in
RX0_MFB_SRC_RDY	std_logic	in
RX0_MFB_DST_RDY	std_logic	out
=====	RX INTERFACE 1	=====	=====
RX1_MVB_HDR	std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)	in
RX1_MVB_PAYLOAD	std_logic_vector(MVB_ITEMS -1 downto 0)	in
RX1_MVB_VLD	std_logic_vector(MVB_ITEMS -1 downto 0)	in
RX1_MVB_SRC_RDY	std_logic	in
RX1_MVB_DST_RDY	std_logic	out
RX1_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	in
RX1_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	in
RX1_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX1_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	in
RX1_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	in
RX1_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	in
RX1_MFB_SRC_RDY	std_logic	in
RX1_MFB_DST_RDY	std_logic	out
=====	TX INTERFACE	=====	=====
TX_MVB_HDR	std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)	out
TX_MVB_PAYLOAD	std_logic_vector(MVB_ITEMS -1 downto 0)	out
TX_MVB_VLD	std_logic_vector(MVB_ITEMS -1 downto 0)	out
TX_MVB_SRC_RDY	std_logic	out
TX_MVB_DST_RDY	std_logic	in
TX_MFB_DATA	std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)	out
TX_MFB_META	std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)	out
TX_MFB_SOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_EOF	std_logic_vector(MFB_REGIONS-1 downto 0)	out
TX_MFB_SOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)	out
TX_MFB_EOF_POS	std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)	out
TX_MFB_SRC_RDY	std_logic	out
TX_MFB_DST_RDY	std_logic	in