MFB FIFOX

ENTITY MFB_FIFOX IS

This component implements the FIFO memory for the MFB interface using the FIFOX component. For more information about the FIFOX component, see the documentation

Generics

Generic	Type	Default	Description
=====	MFB parameters	=====	Frame size restrictions: none
REGIONS	natural	4	any possitive value
REGION_SIZE	natural	8	any possitive value
BLOCK_SIZE	natural	8	any possitive value
ITEM_WIDTH	natural	8
META_WIDTH	natural	0	Metadata width
=====	FIFO parameters	=====	=====
FIFO_DEPTH	natural	512	FIFO depth, number of data words
RAM_TYPE	string	“AUTO”	Select memory implementation. Options: “LUT” - effective when ITEMS <= 64 (on Intel FPGA <= 32), “BRAM” - effective when ITEMS > 64 (on Intel FPGA > 32), “URAM” - effective when ITEMS*FIFO_WIDTH >= 288000 and FIFO_WIDTH >= 72 (URAM is only for Xilinx Ultrascale(+)), “SHIFT” - effective when ITEMS <= 16, “AUTO” - effective implementation dependent on ITEMS and DEVICE.
DEVICE	string	“ULTRASCALE”	Defines what architecture is FIFO implemented on Options: “ULTRASCALE” (Xilinx) “7SERIES” (Xilinx) “ARRIA10” (Intel) “STRATIX10” (Intel)
ALMOST_FULL_OFFSET	natural	1	Determins how many data words left free when almost_full is triggered. (ITEMS - ALMOST_FULL_OFFSET)
ALMOST_EMPTY_OFFSET	natural	1	Determins how many data words present when almost_empty is triggered. (0 + ALMOST_EMPTY_OFFSET)

Ports

Port	Type	Mode	Description
=====	CLOCK AND RESET	=====	=====
CLK	std_logic	in
RST	std_logic	in
=====	RX MFB INTERFACE	=====	=====
RX_DATA	std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)	in
RX_META	std_logic_vector(REGIONS*META_WIDTH-1 downto 0)	in
RX_SOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)	in
RX_EOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)	in
RX_SOF	std_logic_vector(REGIONS-1 downto 0)	in
RX_EOF	std_logic_vector(REGIONS-1 downto 0)	in
RX_SRC_RDY	std_logic	in
RX_DST_RDY	std_logic	out
=====	TX MFB INTERFACE	=====	=====
TX_DATA	std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)	out
TX_META	std_logic_vector(REGIONS*META_WIDTH-1 downto 0)	out
TX_SOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)	out
TX_EOF_POS	std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)	out
TX_SOF	std_logic_vector(REGIONS-1 downto 0)	out
TX_EOF	std_logic_vector(REGIONS-1 downto 0)	out
TX_SRC_RDY	std_logic	out
TX_DST_RDY	std_logic	in
=====	FIFO STATUS SIGNAL	=====	=====
FIFO_STATUS	std_logic_vector(log2(FIFO_DEPTH) downto 0)	out
FIFO_AFULL	std_logic	out
FIFO_AEMPTY	std_logic	out