MFB Splitter
- ENTITY MFB_SPLITTER IS
Splits RX MFB+MVB interface to two intefaces. Switches packets based on one bit SWITCH for each MVB header.
GenericsWarning
Headers and frames are paired by order, not by content. The k-th frame on RX MFB belongs to the k-th header that has
RX_MVB_PAYLOAD(i)='1'. A header with'0'takes no frame.
PortsGeneric
Type
Default
Description
=====
TX MVB characteristics
=====
=====
MVB_ITEMS
integer
2
number of headers
MVB_META_WIDTH
integer
2
width of each MVB meta item
=====
TX MFB characteristics
=====
=====
MFB_REGIONS
integer
2
number of regions in word
MFB_REG_SIZE
integer
1
number of blocks in region
MFB_BLOCK_SIZE
integer
8
number of items in block
MFB_ITEM_WIDTH
integer
32
width of one item (in bits)
=====
Others
=====
=====
HDR_WIDTH
integer
DMA_DOWNHDR_WIDTH
Width of each MVB item DMA_DOWNHDR_WIDTH, DMA_UPHDR_WIDTH
MVB_OUTPUT_FIFO_SIZE
integer
8
Obsolete, use OUT_MVB_FIFO_SIZE instead, which it sets the default of
OUT_MVB_FIFO_SIZE
integer
MVB_OUTPUT_FIFO_SIZE
Depth of the output MVB FIFOs in words Minimum value is 2. They keep the outputs in step with the switch FIFO inside the splitter and cannot be turned off.
IN_MFB_FIFO_EN
boolean
false
Enable an MFB FIFO on the input of the splitter true: Holds the frame back until the header that says where to route it has arrived. A source that puts the header out at the end of the frame needs it. false: Direct connection without input buffering
MFB_FIFO_DEPTH
natural
512
Obsolete, use IN_MFB_FIFO_SIZE instead, which it sets the default of
IN_MFB_FIFO_SIZE
natural
MFB_FIFO_DEPTH
Depth of the input MFB FIFO in words Only used when IN_MFB_FIFO_EN is true
OUT_MFB_FIFO_EN
boolean
false
Enable the output MFB FIFOs. A whole word is routed at once, so without them the slowest output holds up all the others.
OUT_MFB_FIFO_SIZE
natural
512
Depth of the output MFB FIFOs in words Only used when OUT_MFB_FIFO_EN is true
USE_OUTREG
boolean
true
Obsolete, has no effect. The output registers are inside the splitter and are not optional.
DEVICE
string
“ULTRASCALE”
“ULTRASCALE”, “7SERIES”
FIFOX_MULTI_ARCH
string
“SHAKEDOWN”
“FULL”, “SHAKEDOWN”
Port
Type
Mode
Description
=====
Common interface
=====
=====
CLK
std_logic
in
RESET
std_logic
in
=====
RX interface
=====
=====
RX_MVB_HDR
std_logic_vector(MVB_ITEMS*HDR_WIDTH -1 downto 0)
in
RX_MVB_META
std_logic_vector(MVB_ITEMS*MVB_META_WIDTH-1 downto 0)
in
RX_MVB_SWITCH
std_logic_vector(MVB_ITEMS -1 downto 0)
in
output select for each header
RX_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS -1 downto 0)
in
header contains payload in MFB
RX_MVB_VLD
std_logic_vector(MVB_ITEMS -1 downto 0)
in
RX_MVB_SRC_RDY
std_logic
in
RX_MVB_DST_RDY
std_logic
out
RX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
RX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
in
RX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
RX_MFB_SRC_RDY
std_logic
in
RX_MFB_DST_RDY
std_logic
out
=====
TX interface 0
=====
=====
TX0_MVB_HDR
std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)
out
TX0_MVB_META
std_logic_vector(MVB_ITEMS*MVB_META_WIDTH-1 downto 0)
out
TX0_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX0_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX0_MVB_SRC_RDY
std_logic
out
TX0_MVB_DST_RDY
std_logic
in
TX0_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX0_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX0_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX0_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
out
TX0_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX0_MFB_SRC_RDY
std_logic
out
TX0_MFB_DST_RDY
std_logic
in
=====
TX interface 1
=====
=====
TX1_MVB_HDR
std_logic_vector(MVB_ITEMS*HDR_WIDTH-1 downto 0)
out
TX1_MVB_META
std_logic_vector(MVB_ITEMS*MVB_META_WIDTH-1 downto 0)
out
TX1_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX1_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX1_MVB_SRC_RDY
std_logic
out
TX1_MVB_DST_RDY
std_logic
in
TX1_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX1_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX1_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX1_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
out
TX1_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX1_MFB_SRC_RDY
std_logic
out
TX1_MFB_DST_RDY
std_logic
in
MFB Splitter Gen
- ENTITY MFB_SPLITTER_GEN IS
MFB+MVB bus splitter with generic number of outputs.
A single
MFB_SPLITTER_FLATunit routes the input to all outputs in one step, whatever their number. An MFB FIFO can be placed in front of it. Each of its MFB outputs can have anMFB_COMPACTORand an MFB FIFO of its own.With
SPLITTER_OUTPUTSof 1 the input streams are connected straight to output 0. No FIFO, compactor or splitter unit is generated.GenericsWarning
Headers and frames are paired by order, not by content. The k-th frame on RX MFB belongs to the k-th header that has
RX_MVB_PAYLOAD(i)='1'. A header with'0'takes no frame.
PortsGeneric
Type
Default
Description
SPLITTER_OUTPUTS
integer
2
number of splitter outputs
=====
MVB characteristics
=====
=====
MVB_ITEMS
integer
2
number of headers
MVB_ITEM_WIDTH
integer
32
width of header
=====
MFB characteristics
=====
=====
MFB_REGIONS
integer
2
number of regions in word
MFB_REG_SIZE
integer
1
number of blocks in region
MFB_BLOCK_SIZE
integer
8
number of items in block
MFB_ITEM_WIDTH
integer
32
width of one item (in bits)
=====
Others
=====
=====
OUTPUT_FIFO_SIZE
integer
8
Size of output MVB FIFOs (in words) Minimum value is 2! Obsolete, use OUT_MVB_FIFO_SIZE instead. This generic only sets its default value.
IN_MFB_FIFO_EN
boolean
false
Enable the input MFB FIFO. It stores the frame until the header that selects the output has arrived.
IN_MFB_FIFO_SIZE
natural
512
Depth of the input MFB FIFO in words Only used when IN_MFB_FIFO_EN is true
OUT_MVB_FIFO_SIZE
integer
OUTPUT_FIFO_SIZE
Depth of the output MVB FIFOs in words, minimum value is 2. These FIFOs are always generated and keep the headers aligned with the switch FIFO.
OUT_MFB_COMPACTOR_EN
boolean
false
Enable the MFB_COMPACTOR on each output. It removes the Regions that the routing left empty between frames.
OUT_MFB_FIFO_EN
boolean
false
Enable the output MFB FIFOs. All outputs get a word in the same clock cycle, so without these FIFOs the slowest output stops all the others.
MID_MFB_FIFOS_EN
boolean
False
Obsolete, use OUT_MFB_FIFO_EN instead. Setting this generic to true has the same effect.
MFB_FIFO_DEPTH
natural
512
Size of MFB FIFOs (in words) Obsolete, use OUT_MFB_FIFO_SIZE instead. This generic only sets its default value.
OUT_MFB_FIFO_SIZE
natural
MFB_FIFO_DEPTH
Depth of the output MFB FIFOs in words Only used when OUT_MFB_FIFO_EN is true
OUT_PIPE_EN
boolean
true
Obsolete, has no effect.
DEVICE
string
“ULTRASCALE”
“ULTRASCALE”, “STRATIX10”,…
FIFOX_MULTI_ARCH
string
“SHAKEDOWN”
“FULL”, “SHAKEDOWN”
Port
Type
Mode
Description
=====
Common interface
=====
=====
CLK
std_logic
in
RESET
std_logic
in
=====
RX interfaces
=====
=====
RX_MVB_DATA
std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
in
RX_MVB_SWITCH
std_logic_vector(MVB_ITEMS*log2(SPLITTER_OUTPUTS)-1 downto 0)
in
output select for each header
RX_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS-1 downto 0)
in
the header is associated with a payload frame on MFB
RX_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
in
RX_MVB_SRC_RDY
std_logic
in
RX_MVB_DST_RDY
std_logic
out
RX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
RX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
in
RX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
RX_MFB_SRC_RDY
std_logic
in
RX_MFB_DST_RDY
std_logic
out
=====
TX interface
=====
=====
TX_MVB_DATA
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
out
TX_MVB_PAYLOAD
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)
out
the header is associated with a payload frame on MFB
TX_MVB_VLD
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)
out
TX_MVB_SRC_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
out
TX_MVB_DST_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
in
TX_MFB_DATA
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX_MFB_SOF
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)
out
TX_MFB_EOF
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)
out
TX_MFB_SOF_POS
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
out
TX_MFB_EOF_POS
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX_MFB_SRC_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
out
TX_MFB_DST_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
in
MFB Splitter Flat
- ENTITY MFB_SPLITTER_FLAT IS
MFB+MVB bus splitter which routes to all its outputs in a single step.
Splits one input MVB+MFB stream into
SPLITTER_OUTPUTSoutput streams.Warning
Headers and frames are paired by order, not by content. The k-th frame on RX MFB belongs to the k-th header that has
RX_MVB_PAYLOAD(i)='1'. A header with'0'takes no frame.How it works
Headers and payload are routed by two halves of this component, kept in step by the switch FIFO.
The MVB half is a plain demultiplexer.
RX_MVB_SWITCHsays which output each header goes to, so the header is written into that output’s MVB FIFO. Every header that announces a payload also writes its output number into the switch FIFO. That FIFO holds one item per packet, in the order the packets arrive on MFB.The MFB half follows the switch FIFO. A word may carry one packet per Region, so it takes as many items as the word has SOFs. Each Region is handed the output number of the packet it belongs to, and
GenericsMFB_SPLITTER_SIMPLE_GENdoes the routing. A word only passes once the FIFO holds an item for every SOF in it. Otherwise the MFB half would route a packet whose header has not arrived yet.
PortsGeneric
Type
Default
Description
SPLITTER_OUTPUTS
natural
4
Number of splitter output streams, must be at least 2
MVB_ITEMS
natural
2
Number of MVB headers per word
MVB_ITEM_WIDTH
natural
32
Width of one MVB header in bits
MFB_REGIONS
natural
2
Number of Regions per MFB word
MFB_REG_SIZE
natural
1
Number of Blocks per Region
MFB_BLOCK_SIZE
natural
8
Number of Items per Block
MFB_ITEM_WIDTH
natural
32
Width of one MFB Item in bits
OUT_MVB_FIFO_SIZE
natural
8
Depth of the output MVB FIFOs in words, minimum value is 2. These FIFOs are always generated and keep the headers aligned with the switch FIFO.
FIFOX_MULTI_ARCH
string
“SHAKEDOWN”
Architecture of the internal FIFOX_MULTI, “SHAKEDOWN” or “FULL”
DEVICE
string
“ULTRASCALE”
Target device family
Port
Type
Mode
Description
=====
COMMON SIGNALS
=====
=====
CLK
std_logic
in
RESET
std_logic
in
=====
RX INTERFACE
=====
=====
RX_MVB_DATA
std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
in
RX_MVB_SWITCH
std_logic_vector(MVB_ITEMS*log2(SPLITTER_OUTPUTS)-1 downto 0)
in
Output select for each header, valid with RX_MVB_VLD
RX_MVB_PAYLOAD
std_logic_vector(MVB_ITEMS-1 downto 0)
in
The header is associated with a payload frame on MFB
RX_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
in
RX_MVB_SRC_RDY
std_logic
in
RX_MVB_DST_RDY
std_logic
out
RX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
RX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
in
RX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
RX_MFB_SRC_RDY
std_logic
in
RX_MFB_DST_RDY
std_logic
out
=====
TX INTERFACES (per output port)
=====
=====
TX_MVB_DATA
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
out
TX_MVB_PAYLOAD
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)
out
TX_MVB_VLD
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MVB_ITEMS-1 downto 0)
out
TX_MVB_SRC_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
out
TX_MVB_DST_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
in
TX_MFB_DATA
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX_MFB_SOF
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)
out
TX_MFB_EOF
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS-1 downto 0)
out
TX_MFB_SOF_POS
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0)
out
TX_MFB_EOF_POS
slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX_MFB_SRC_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
out
TX_MFB_DST_RDY
std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)
in