MFB MVB Appender
- ENTITY MFB_MVB_APPENDER IS
This component appends input MVB Items to packets (moves EOF). Its simple architecture utilizes MFB reconfigurators: Input MFB words are first reconfigured to MFB#(1,1,MFB_REGION_SIZE*MFB_BLOCK_SIZE,MFB_ITEM_WIDTH), so SOFs are aligned to the start of word (MFB Block 0). The appending process occurs in two steps:
MVB append data are inserted onto a (temporary) MFB word and shifted according to the EOF (POS) of the original packet.
This word is multiplexed with the MFB word containing the original packet according to the so-called “append vector”, which contains 1s from the EOF of the original packet to the offset created by the append data.
Warning
In this first version, the component has certain limitations:
Only one MFB Region is supported. Multiple MFB Reagions are difficult to handle for the shifting mechanism.
MVB Items cannot be wider than the MFB word. This would also cause problems for the shifting mechanism.
Further versions could remove these limitations. They could also utilize MFB Frame Masker instead of the Reconfigurators.
Generics
PortsGeneric
Type
Default
Description
MFB_REGIONS
natural
1
Number of Regions within a data word, must be power of 2. In this version, only one MFB Region is supported.
MFB_REGION_SIZE
natural
8
Region size (in Blocks).
MFB_BLOCK_SIZE
natural
8
Block size (in Items), must be 8.
MFB_ITEM_WIDTH
natural
8
Item width (in bits), must be 8.
MFB_META_WIDTH
natural
0
Metadata width (in bits).
PKT_MTU_IN
natural
2**14
Maximum size of input packets (in Items). Output packets’ MTU is PKT_MTU_IN + MVB_ITEM_SIZE.
MVB_ITEMS
natural
1
Number of MVB Items in one word.
MVB_ITEM_SIZE
natural
16
Size of each MVB Item (in MFB Items!). MVB_ITEMS*MVB_ITEM_SIZE must not be greater than the number of MFB Items in a word (MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE).
MFB_FIFO_DEPTH
natural
32
Number of Items in the Input MFB_FIFOX.
APPEND_FIFO_DEPTH
natural
32
Number of Items in the Input APPEND FIFOX.
RX_MFB_CONF_EQ_TX
boolean
True
Whether the input and output MFB configurations are the same. If “false”, TX MFB configuration is 1,1,MFB_REGION_SIZE*MFB_BLOCK_SIZE,MFB_ITEM_WIDTH. Disabling backward configuration saves resources.
DEVICE
string
“STRATIX10”
FPGA device name: ULTRASCALE, STRATIX10, AGILEX, …
Port
Type
Mode
Description
=====
Clock and Reset
=====
=====
CLK
std_logic
in
RESET
std_logic
in
=====
RX MFB inf
=====
=====
RX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
RX_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
in
Valid with SOF.
RX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)
in
RX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
in
RX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
in
RX_MFB_SRC_RDY
std_logic
in
RX_MFB_DST_RDY
std_logic
out
=====
RX MVB inf (append data)
=====
=====
RX_MVB_DATA
std_logic_vector(MVB_ITEMS*MVB_ITEM_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
RX_MVB_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
in
RX_MVB_SRC_RDY
std_logic
in
RX_MVB_DST_RDY
std_logic
out
=====
TX MFB inf (frames with appended MVB data)
=====
=====
TX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
out
TX_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
out
Valid with SOF.
TX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(tsel(RX_MFB_CONF_EQ_TX, MFB_REGION_SIZE, 1)))-1 downto 0)
out
TX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
out
TX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX_MFB_EOF
std_logic_vector(MFB_REGIONS-1 downto 0)
out
TX_MFB_SRC_RDY
std_logic
out
TX_MFB_DST_RDY
std_logic
in