MVB FIFOX

ENTITY MVB_FIFOX IS

Synchronous (single clock domain) general-purpose FIFO for the MVB bus, implemented as a thin wrapper around the generic FIFOX component. The MVB item validity (RX_VLD/TX_VLD) is stored together with RX_DATA/TX_DATA in the same memory word. The TX side behaves as First-Word-Fall-Through: valid data is presented on TX_DATA/TX_VLD together with TX_SRC_RDY without needing a prior TX_DST_RDY request; a write takes at least two CLK cycles before the written word can appear on the TX side.

Note

When FAKE_FIFO = true, the FIFO memory is not instantiated; RX and TX are connected combinationally (TX_DATA/TX_VLD = RX_DATA/RX_VLD, TX_SRC_RDY = RX_SRC_RDY, RX_DST_RDY = TX_DST_RDY) with zero latency. Unlike some other FIFO wrappers in this repository, this passthrough still correctly propagates TX-side backpressure to RX_DST_RDY, so it is always safe to use, not only when the TX side is always ready.

Generics

Generic	Type	Default	Description
ITEMS	natural	4	Number of MVB items transferred in one word.
ITEM_WIDTH	natural	8	Width of one MVB item in bits.
FIFO_DEPTH	natural	512	FIFO depth in number of data words.
RAM_TYPE	string	“AUTO”	Select memory implementation. Options: “LUT” - effective when FIFO_DEPTH <= 64 (on Intel FPGA <= 32) “BRAM” - effective when FIFO_DEPTH > 64 (on Intel FPGA > 32) “URAM” - effective when FIFO_DEPTH * (ITEMS*ITEM_WIDTH+ITEMS) >= 288000 and (ITEMS*ITEM_WIDTH+ITEMS) >= 72 (URAM is only available on DEVICE = “ULTRASCALE” or “VERSAL”) “SHIFT” - effective when FIFO_DEPTH <= 16 “AUTO” - implementation chosen automatically based on FIFO_DEPTH and DEVICE
DEVICE	string	“ULTRASCALE”	Defines what architecture the FIFO is implemented on. Options: “ULTRASCALE”, “7SERIES”, “VERSAL” (Xilinx) “ARRIA10”, “STRATIX10”, “AGILEX” (Intel)
ALMOST_FULL_OFFSET	natural	1	Determines how many free data words remain when AFULL is triggered. (currently_stored >= FIFO_DEPTH - ALMOST_FULL_OFFSET)
ALMOST_EMPTY_OFFSET	natural	1	Determines how many stored data words remain when AEMPTY is triggered. (currently_stored <= ALMOST_EMPTY_OFFSET)
FAKE_FIFO	boolean	false	Disables the FIFO implementation and replaces it with straight wires, see the NOTE above.

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
=====	RX INTERFACE	=====	=====
RX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	in
RX_VLD	std_logic_vector(ITEMS-1 downto 0)	in
RX_SRC_RDY	std_logic	in
RX_DST_RDY	std_logic	out
=====	TX INTERFACE	=====	=====
TX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	out
TX_VLD	std_logic_vector(ITEMS-1 downto 0)	out
TX_SRC_RDY	std_logic	out
TX_DST_RDY	std_logic	in
=====	STATUS FLAGS	=====	=====
STATUS	std_logic_vector(log2(FIFO_DEPTH) downto 0)	out	Number of words currently stored in the FIFO (not the number of free words). Held at ‘0’ when FAKE_FIFO = true.
AFULL	std_logic	out
AEMPTY	std_logic	out