MVB ASFIFOX

ENTITY MVB_ASFIFOX IS

Asynchronous (independent RX/TX clock domain) FIFO for the MVB bus, implemented as a thin wrapper around the generic ASFIFOX component. The MVB item validity (RX_VLD/TX_VLD) is stored together with RX_DATA/TX_DATA in the same memory word, so both cross the clock-domain boundary atomically.

Warning

RX_RESET and TX_RESET are combined internally (by the underlying ASFIFOX core) into a single reset of the whole FIFO, synchronized separately into each clock domain. Asserting either one resets both the write and the read side; they are not independent per-side resets.

Generics

Generic	Type	Default	Description
MVB_ITEMS	integer	4	Number of MVB items transferred in one word.
MVB_ITEM_WIDTH	integer	8	Width of one MVB item in bits. Any positive value.
FIFO_ITEMS	natural	512	FIFO depth in number of data words. Must be a power of two, minimum value is 2.
RAM_TYPE	string	“BRAM”	Select memory implementation: “LUT” - distributed/LUT memory, effective for a shallow FIFO (approx. FIFO_ITEMS <= 64). “BRAM” - block RAM, effective for a deep FIFO (approx. FIFO_ITEMS > 64). “AUTO” - treated the same as “BRAM” by the underlying core.
FWFT_MODE	boolean	True	First Word Fall Through mode. If true, valid data is ready at TX_DATA/TX_VLD (TX_SRC_RDY = ‘1’) without TX_DST_RDY having to be asserted first. Warning Setting this to false removes the automatic advance into the output register: the core then only reads a new word in direct response to TX_DST_RDY, so TX_DST_RDY must already be asserted one or more cycles before TX_SRC_RDY becomes valid for that word (unlike the default, where TX_SRC_RDY becomes valid on its own and TX_DST_RDY is only needed to accept/advance past it).
OUTPUT_REG	boolean	True	Adds one more register stage between the internal memory’s read output and TX_DATA/TX_VLD/TX_SRC_RDY. Improves timing at the cost of a few more flip-flops and one additional TX_CLK cycle of latency between writing a word (RX side) and it becoming valid on the TX side.
DEVICE	string	“ULTRASCALE”	Target FPGA device, passed through to the underlying memory implementation (affects the “LUT” RAM_TYPE only, where it selects the correct distributed/MLAB memory primitive). “7SERIES”, “ULTRASCALE”, “VERSAL”, “STRATIX10”, “ARRIA10”, “AGILEX”
ALMOST_FULL_OFFSET	natural	FIFO_ITEMS/2	Number of free words (write/RX side) at or below which RX_AFULL is asserted.
ALMOST_EMPTY_OFFSET	natural	FIFO_ITEMS/2	Number of stored words (read/TX side) at or below which TX_AEMPTY is asserted.

Ports

Port	Type	Mode	Description
=====	RX INTERFACE (write side, RX_CLK domain)	=====	=====
RX_CLK	std_logic	in
RX_RESET	std_logic	in
RX_DATA	std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)	in
RX_VLD	std_logic_vector(MVB_ITEMS-1 downto 0)	in
RX_SRC_RDY	std_logic	in
RX_DST_RDY	std_logic	out
RX_AFULL	std_logic	out	Asserted when the number of free words drops to or below ALMOST_FULL_OFFSET.
RX_STATUS	std_logic_vector(log2(FIFO_ITEMS) downto 0)	out	Number of words currently stored in the FIFO (write/RX side view).
=====	TX INTERFACE (read side, TX_CLK domain - independent of RX_CLK)	=====	=====
TX_CLK	std_logic	in
TX_RESET	std_logic	in
TX_DATA	std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)	out
TX_VLD	std_logic_vector(MVB_ITEMS-1 downto 0)	out
TX_SRC_RDY	std_logic	out
TX_DST_RDY	std_logic	in
TX_AEMPTY	std_logic	out	Asserted when the number of stored words drops to or below ALMOST_EMPTY_OFFSET.
TX_STATUS	std_logic_vector(log2(FIFO_ITEMS) downto 0)	out	Number of words currently stored in the FIFO (read/TX side view); may be nonzero even before the data appears on TX_DATA/TX_VLD.