MVB FIFO

ENTITY MVB_FIFO IS

Synchronous (single clock domain) general-purpose FIFO for the MVB bus. Selects between a distributed/LUT-RAM-based core and a BlockRAM-based core (see USE_BRAMS). The TX side always behaves as First-Word-Fall-Through, i.e. valid data is presented on TX_DATA/TX_VLD together with TX_SRC_RDY as soon as it is available, without needing a prior TX_DST_RDY request.

Warning

When USE_DST_RDY = false, no FIFO memory is instantiated at all: the component becomes a pure combinational pass-through (RX_DATA/RX_VLD/ RX_SRC_RDY wired directly to TX_DATA/TX_VLD/TX_SRC_RDY), RX_DST_RDY is tied permanently to ‘1’ and TX_DST_RDY is completely ignored. Use this mode only where the TX-side consumer is guaranteed to always be ready; otherwise data is silently lost.

Generics

Generic	Type	Default	Description
ITEMS	integer	4	Number of MVB items transferred in one word. Any positive value.
ITEM_WIDTH	integer	8	Width of one MVB item in bits. Any positive value.
USE_DST_RDY	boolean	true	Enables destination-ready (backpressure) handling and the actual FIFO storage memory. See the WARNING above for the false case.
USE_BRAMS	boolean	false	Select memory implementation (only relevant when USE_DST_RDY = true): true - BlockRAM-based core (FIFO_BRAM); preferable for larger FIFO_ITEMS depths. false - distributed/LUT-RAM-based core (FIFO, “SelectRAM”); preferable for small FIFO_ITEMS depths, avoids consuming a whole BRAM.
FIFO_ITEMS	integer	64	FIFO depth in number of data words. Any integer value of 2 or more; does not need to be a power of two.
BLOCK_SIZE	integer	1	Size, in items, of one write “block” used for the LSTBLK flag. LSTBLK is asserted once the remaining free capacity drops to BLOCK_SIZE items, signalling a block-oriented producer that only one more block of this size can still be safely written.
STATUS_ENABLED	boolean	true	Enables the internal free-space counter that drives STATUS (and, together with BLOCK_SIZE, LSTBLK). The counter is only skipped (saving a few resources) when STATUS_ENABLED = false and BLOCK_SIZE = 0 at the same time - BLOCK_SIZE defaults to 1, so STATUS/LSTBLK are valid by default even with STATUS_ENABLED = false. See the STATUS/LSTBLK port descriptions for what happens when the counter is skipped.
OUTPUT_REG	boolean	true	Adds an output register stage on the TX_DATA/TX_VLD path for better timing, at the cost of extra registers and one additional clock cycle of latency.

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
=====	RX INTERFACE	=====	=====
RX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	in
RX_VLD	std_logic_vector(ITEMS-1 downto 0)	in
RX_SRC_RDY	std_logic	in
RX_DST_RDY	std_logic	out
=====	TX INTERFACE	=====	=====
TX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	out
TX_VLD	std_logic_vector(ITEMS-1 downto 0)	out
TX_SRC_RDY	std_logic	out
TX_DST_RDY	std_logic	in
=====	STATUS FLAGS	=====	=====
LSTBLK	std_logic	out	When the free-space counter is skipped (see STATUS_ENABLED above): held at ‘0’ if USE_BRAMS = false, but left completely undriven (undefined in simulation) if USE_BRAMS = true - avoid that combination if LSTBLK is used.
FULL	std_logic	out	Equivalent to “not RX_DST_RDY”.
EMPTY	std_logic	out	Equivalent to “not TX_SRC_RDY” when USE_BRAMS = false. When USE_BRAMS = true, EMPTY deasserts one CLK cycle before TX_SRC_RDY asserts (two cycles when OUTPUT_REG = true), because of the BlockRAM output-register read pipeline latency; use TX_SRC_RDY, not EMPTY, to determine data validity on the TX side.
STATUS	std_logic_vector(log2(FIFO_ITEMS) downto 0)	out	Number of currently free (unoccupied) words in the FIFO - not the number of stored words. Held at ‘0’ when the free-space counter is skipped (see STATUS_ENABLED above).