MVB Gate

ENTITY MVB_GATE IS

Simple gate for MVB bus. Has option for instation of FIFO, which can smooth out stopping of the bus.

Generics

Generic	Type	Default	Description
ITEMS	natural	4
ITEM_WIDTH	natural	8
RX_FIFO_EN	boolean	false
RX_FIFO_DEPTH	natural	32
DEVICE	string	“AGILEX”

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
=====	RX MVB interface	=====	=====
RX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	in
RX_VLD	std_logic_vector(ITEMS-1 downto 0)	in
RX_SRC_RDY	std_logic	in
RX_DST_RDY	std_logic	out
=====	TX MVB interface	=====	=====
TX_DATA	std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0)	out
TX_VLD	std_logic_vector(ITEMS-1 downto 0)	out
TX_SRC_RDY	std_logic	out
TX_DST_RDY	std_logic	in
=====	Control interface	=====	=====
STOP_EN	std_logic	in	When this signal is asserted, transmission from RX -> TX is disabled.