MVB Merge Streams
- ENTITY MVB_MERGE_STREAMS IS
The MVB_MERGE_STREAMS component is used to merge two or more independent MVB streams into one. The order of merging items is random. A stream is switched after a set number of transferred words (parameter SW_TIMEOUT_W) or as soon as it runs empty. Better transmission efficiency can be achieved by enabling input MVB SHAKEDOWNS (parameter RX_SHAKEDOWN_EN).
Generics
PortsGeneric
Type
Default
Description
MVB_ITEMS
natural
4
Number of MVB items
MVB_ITEM_WIDTH
natural
32
MVB item width in bits
RX_STREAMS
natural
2
Number of input MVB streams, must be power of two
RX_SHAKEDOWN_EN
boolean
True
Enable MVB SHAKEDOWN on each MVB input stream
SW_TIMEOUT_W
natural
4
Width of the timeout counter. It counts transferred words, so one stream is served for 2**(SW_TIMEOUT_W-1) words.
DEVICE
string
“AGILEX”
FPGA device string
Port
Type
Mode
Description
CLK
std_logic
in
Clock input
RESET
std_logic
in
Reset input synchronized with CLK
RX_DATA
slv_array_t(RX_STREAMS-1 downto 0)(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
in
RX MVB: data word with MVB items
RX_VLD
slv_array_t(RX_STREAMS-1 downto 0)(MVB_ITEMS-1 downto 0)
in
RX MVB: valid of each MVB item
RX_SRC_RDY
std_logic_vector(RX_STREAMS-1 downto 0)
in
RX MVB: source ready
RX_DST_RDY
std_logic_vector(RX_STREAMS-1 downto 0)
out
RX MVB: destination ready
TX_DATA
std_logic_vector(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
out
TX MVB: data word with MVB items
TX_VLD
std_logic_vector(MVB_ITEMS-1 downto 0)
out
TX MVB: valid of each MVB item
TX_SRC_RDY
std_logic
out
TX MVB: source ready
TX_DST_RDY
std_logic
in
TX MVB: destination ready