MI2AXI4

ENTITY MI2AXI4 IS

This component converts MI interface (slave) to AXI4 interface (master).

Generics

Generic	Type	Default	Description
MI_DATA_WIDTH	natural	32	MI data word width in bits, must be 32
AXI_DATA_WIDTH	natural	64	AXI data word width in bits, 32 or 64
ADDR_WIDTH	natural	32	Address word width in bits
ADDR_MASK	std_logic_vector(ADDR_WIDTH-1 downto 0)	(others => ‘1’)	Address mask vector
DEVICE	string	“AGILEX”	Target device

Ports

Port	Type	Mode	Description
=====	Clock and Reset	=====	=====
CLK	std_logic	in
RESET	std_logic	in
=====	MI interface (slave)	=====	=====
MI_DWR	std_logic_vector(MI_DATA_WIDTH-1 downto 0)	in
MI_ADDR	std_logic_vector(ADDR_WIDTH-1 downto 0)	in
MI_RD	std_logic	in
MI_WR	std_logic	in
MI_BE	std_logic_vector((MI_DATA_WIDTH/8)-1 downto 0)	in
MI_DRD	std_logic_vector(MI_DATA_WIDTH-1 downto 0)	out
MI_ARDY	std_logic	out
MI_DRDY	std_logic	out
=====	AXI4 interface (master)	=====	=====
AXI_AWID	std_logic_vector(8-1 downto 0)	out
AXI_AWADDR	std_logic_vector(ADDR_WIDTH-1 downto 0)	out
AXI_AWLEN	std_logic_vector(8-1 downto 0)	out
AXI_AWSIZE	std_logic_vector(3-1 downto 0)	out
AXI_AWBURST	std_logic_vector(2-1 downto 0)	out
AXI_AWPROT	std_logic_vector(3-1 downto 0)	out
AXI_AWVALID	std_logic	out
AXI_AWREADY	std_logic	in
AXI_WDATA	std_logic_vector(AXI_DATA_WIDTH-1 downto 0)	out
AXI_WSTRB	std_logic_vector((AXI_DATA_WIDTH/8)-1 downto 0)	out
AXI_WVALID	std_logic	out
AXI_WREADY	std_logic	in
AXI_BID	std_logic_vector(8-1 downto 0)	in
AXI_BRESP	std_logic_vector(2-1 downto 0)	in
AXI_BVALID	std_logic	in
AXI_BREADY	std_logic	out
AXI_ARID	std_logic_vector(8-1 downto 0)	out
AXI_ARADDR	std_logic_vector(ADDR_WIDTH-1 downto 0)	out
AXI_ARLEN	std_logic_vector(8-1 downto 0)	out
AXI_ARSIZE	std_logic_vector(3-1 downto 0)	out
AXI_ARBURST	std_logic_vector(2-1 downto 0)	out
AXI_ARPROT	std_logic_vector(3-1 downto 0)	out
AXI_ARVALID	std_logic	out
AXI_ARREADY	std_logic	in
AXI_RID	std_logic_vector(8-1 downto 0)	in
AXI_RDATA	std_logic_vector(AXI_DATA_WIDTH-1 downto 0)	in
AXI_RRESP	std_logic_vector(2-1 downto 0)	in
AXI_RLAST	std_logic	in
AXI_RVALID	std_logic	in
AXI_RREADY	std_logic	out