MI2AVMM
- ENTITY MI2AVMM IS
This component converts MI interface to Avalon Memory-Mapped (Avalon-MM) interface. In the current implementation these are just directly connected wires and one not gate.
Generics
PortsGeneric
Type
Default
Description
DATA_WIDTH
natural
32
Data word width in bits
ADDR_WIDTH
natural
32
Address word width in bits
META_WIDTH
natural
2
Meta word width in bits
DEVICE
string
“AGILEX”
Target device (Intel only) (UNUSED)
Port
Type
Mode
Description
CLK
std_logic
in
RESET
std_logic
in
MI_DWR
std_logic_vector(DATA_WIDTH-1 downto 0)
in
Input Data
MI_MWR
std_logic_vector(META_WIDTH-1 downto 0)
in
Input Metadata (not used yet)
MI_ADDR
std_logic_vector(ADDR_WIDTH-1 downto 0)
in
Address
MI_RD
std_logic
in
Read Request
MI_WR
std_logic
in
Write Request
MI_BE
std_logic_vector((DATA_WIDTH/8)-1 downto 0)
in
Byte Enable
MI_DRD
std_logic_vector(DATA_WIDTH-1 downto 0)
out
Output Data
MI_ARDY
std_logic
out
Address Ready
MI_DRDY
std_logic
out
Data Ready
AVMM_ADDRESS
std_logic_vector(ADDR_WIDTH-1 downto 0)
out
Address
AVMM_WRITE
std_logic
out
Write Request
AVMM_READ
std_logic
out
Read Request
AVMM_BYTEENABLE
std_logic_vector((DATA_WIDTH/8)-1 downto 0)
out
Byte Enable
AVMM_WRITEDATA
std_logic_vector(DATA_WIDTH-1 downto 0)
out
Output Data
AVMM_READDATA
std_logic_vector(DATA_WIDTH-1 downto 0)
in
Input Data
AVMM_READDATAVALID
std_logic
in
Input Data Valid
AVMM_WAITREQUEST
std_logic
in
Wait Request
Read MI bus specification for more information on the MI bus.
Specification
Both interfaces use common clock and reset signals. AVMM interface does not support debugaccess, optional signals (response, writeresponsevalid), lock for multiple hosts and burst mode signals (burstcount, beginbursttransfer). Pipelined read transfers are possible with readdatavalid signal. According to the Avalon-MM specification, there must be at least one cycle of latency between acceptance of the read signal and assertion of readdatavalid (in opposite to MI bus DRDY signal with possible 0 cycle latency). waitrequest signal is asserted when the component is unable to accept data, thus the data must be kept constant until the signal is deasserted (MI bus ARDY signal negation).
Warning
The waitrequestAllowance property is the number of transfers accepted after assertion of waitrequest signal. The only supported value of this property is 0.
Warning
This component only supports data with the same width on both sides (32 bits by default). These are addressed as one unit (e.g. when using 32 bit data, byte adresses 0x00 to 0x03 will be on OFFSET[0], 0x04 to 0x07 on OFFSET[1]).
Refer to Avalon Interface Specification for more information on Avalon-MM interfaces (see section 3).