MI ASYNC
- ENTITY MI_ASYNC IS
The MI_ASYNC implements the MI bus transition between two clock domains. Asynchronous FIFO memory is used to implement the cross-domain crossing. The MI_ASYNC component also contains logic that can ensure the correct behavior of the MI bus in the event of an unexpected reset in only one clock domain (see RESET_LOGIC generic).
Generics
PortsGeneric
Type
Default
Description
DATA_WIDTH
natural
32
Data word width in bits, must be power of 2.
ADDR_WIDTH
natural
32
Address word width in bits.
META_WIDTH
natural
2
Meta word width in bits.
RAM_TYPE
string
“LUT”
Select memory implementation. Options: “LUT” or “BRAM”
RESET_LOGIC
boolean
true
RESET_LOGIC provides additional logic for safe asynchronous reset of the component when one or both of the sides are in reset state, without violating MI protocol
DEVICE
string
“ULTRASCALE”
The DEVICE parameter allows the correct selection of the RAM implementation according to the FPGA used.
Port
Type
Mode
Description
CLK_M
std_logic
in
Master interface: Clock
RESET_M
std_logic
in
Master interface: Reset
MI_M_DWR
std_logic_vector(DATA_WIDTH-1 downto 0)
in
Master interface: MI Write Data
MI_M_MWR
std_logic_vector(META_WIDTH-1 downto 0)
in
Master interface: MI Write Metadata
MI_M_ADDR
std_logic_vector(ADDR_WIDTH-1 downto 0)
in
Master interface: MI Address
MI_M_RD
std_logic
in
Master interface: MI Read Request
MI_M_WR
std_logic
in
Master interface: MI Write Request
MI_M_BE
std_logic_vector((DATA_WIDTH/8)-1 downto 0)
in
Master interface: Byte Enable
MI_M_DRD
std_logic_vector(DATA_WIDTH-1 downto 0)
out
Master interface: MI Read Data
MI_M_ARDY
std_logic
out
Master interface: MI Address Ready
MI_M_DRDY
std_logic
out
Master interface: MI Read Data Ready
CLK_S
std_logic
in
Slave interface: Clock
RESET_S
std_logic
in
Slave interface: Reset
MI_S_DWR
std_logic_vector(DATA_WIDTH-1 downto 0)
out
Slave interface: MI Write Data
MI_S_MWR
std_logic_vector(META_WIDTH-1 downto 0)
out
Slave interface: MI Write Metadata
MI_S_ADDR
std_logic_vector(ADDR_WIDTH-1 downto 0)
out
Slave interface: MI Address
MI_S_RD
std_logic
out
Slave interface: MI Read Request
MI_S_WR
std_logic
out
Slave interface: MI Write Request
MI_S_BE
std_logic_vector((DATA_WIDTH/8)-1 downto 0)
out
Slave interface: Byte Enable
MI_S_DRD
std_logic_vector(DATA_WIDTH-1 downto 0)
in
Slave interface: MI Read Data
MI_S_ARDY
std_logic
in
Slave interface: MI Address Ready
MI_S_DRDY
std_logic
in
Slave interface: MI Read Data Ready