MI indirect access
Through this component it is possible to send MI transactions indirectly to one or more output interfaces. That means you have to set the parameters of the MI transaction (by sending Write requests) to a set of registers, which are also accessed by MI.
- ENTITY MI_INDIRECT_ACCESS IS
- Generics
PortsGeneric
Type
Default
Description
DATA_WIDTH
natural
32
Width of MI data
ADDR_WIDTH
natural
32
Width of MI address
OUTPUT_INTERFACES
natural
3
Number of output interfaces
Port
Type
Mode
Description
=====
Common interface
=====
=====
CLK
std_logic
in
RESET
std_logic
in
=====
Input MI interface
=====
=====
RX_ADDR
std_logic_vector(ADDR_WIDTH-1 downto 0)
in
RX_DWR
std_logic_vector(DATA_WIDTH-1 downto 0)
in
RX_WR
std_logic
in
RX_RD
std_logic
in
RX_ARDY
std_logic
out
RX_DRD
std_logic_vector(DATA_WIDTH-1 downto 0)
out
RX_DRDY
std_logic
out
=====
Output MI interface
=====
=====
TX_ADDR
slv_array_t (OUTPUT_INTERFACES-1 downto 0)(DATA_WIDTH-1 downto 0)
out
TX_DWR
slv_array_t (OUTPUT_INTERFACES-1 downto 0)(DATA_WIDTH-1 downto 0)
out
TX_WR
std_logic_vector(OUTPUT_INTERFACES-1 downto 0)
out
TX_RD
std_logic_vector(OUTPUT_INTERFACES-1 downto 0)
out
TX_ARDY
std_logic_vector(OUTPUT_INTERFACES-1 downto 0)
in
TX_DRD
slv_array_t (OUTPUT_INTERFACES-1 downto 0)(DATA_WIDTH-1 downto 0)
in
TX_DRDY
std_logic_vector(OUTPUT_INTERFACES-1 downto 0)
in
Warning
Check the status bit before sending each request to avoid possible errors. The LSB of the Status register indicates business of the component- if set high, the component is busy and you must not send any requests.
You can, of course, send Read requests addressed to the Status register to check the current status of the component.
Usage
Set the ID of the desired output interface, Address , Data to be written (in case it’s a Write reqest), and the Command of the indirect request. Set LSB of the Command register (cmd(0)) to ‘1’ to send indirect Write request or set cmd(1) to ‘1’ to send indirect Read request.
Warning
The indirect request will be sent immediately after recieving a command, so you must set this register last.
Address space
Register |
Address |
|---|---|
Output interface |
0x00 |
Address |
0x04 |
Write data |
0x08 |
Read data |
0x0C |
Command |
0x10 |
Status |
0x14 |