Memory clear

Simple component that will generate addresses for memory clearing when RST is asserted.

Component port and generics description

ENTITY MEM_CLEAR IS

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RST	std_logic	in
CLEAR_DONE	std_logic	out	All addresses were generated
CLEAR_WR	std_logic	out	Clear address given by CLEAR_ADDR
CLEAR_ADDR	std_logic_vector(log2(ITEMS) - 1 downto 0)	out

Instance template

data_clear_i : entity work.MEM_CLEAR
generic map (
    DATA_WIDTH  => BOX_WIDTH,
    ITEMS       => BOX_CNT,
    CLEAR_EN    => CLEAR_BY_RST
)
port map (
    CLK         => CLK,
    RST         => RST,

    CLEAR_DONE  => RST_DONE,
    CLEAR_WR    => wr_clear,
    CLEAR_ADDR  => wr_addr_clear
);