MVB Merge Streams Ordered
- ENTITY MVB_MERGE_STREAMS_ORDERED IS
Merges multiple MVB streams to one big streams in defined order. Order is defined by RX_SEL interface. Each word on this interface tells from which interface next word should be transmitted. Words are transmitted exacly as defined on RX_SEL interface, i.e. when RX_SEL word at position 1 is 2, at position 2 is 3, TX interface will contain word from RX interface 2 at position 1 and word from RX interface 3 at position 2. There are no constraints on RX_SEL interface - all selects can be from same RX interface.
Generics
PortsGeneric
Type
Default
Description
MVB_ITEMS
natural
1
Number of MVB items
MVB_ITEM_WIDTH
natural
32
MVB item width in bits
RX_STREAMS
natural
4
Number of input MVB streams, must be power of two
USE_FIFOX_MULTI
boolean
true
Use FIFOX multi instead of shakedown to improve on efficiency and buffering. Costs more resources.
FIFOX_ITEMS_MULT
natural
4
Fifox multi items multiplier, should be power of 2. Defines total capacity of FIFOX MULTI by expression: MVB_ITEMS * RX_STREAMS * FIFOX_ITEMS_MULT. Ignored when USE_FIFOX_MULTI is false.
SEL_SHAKEDOWN_EN
boolean
true
Enable shakedown on RX SEL MVB interface. Can improve throughput by accumulating sparse selects to dense ones. More effective with FIFOX MULTI enabled.
DEVICE
string
“AGILEX”
FPGA device string
Port
Type
Mode
Description
CLK
std_logic
in
Clock input
RESET
std_logic
in
Reset input synchronized with CLK
RX_DATA
slv_array_t(RX_STREAMS-1 downto 0)(MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
in
RX MVB: data word with MVB items
RX_VLD
slv_array_t(RX_STREAMS-1 downto 0)(MVB_ITEMS-1 downto 0)
in
RX MVB: valid of each MVB item
RX_SRC_RDY
std_logic_vector(RX_STREAMS-1 downto 0)
in
RX MVB: source ready
RX_DST_RDY
std_logic_vector(RX_STREAMS-1 downto 0)
out
RX MVB: destination ready
RX_SEL_IF
std_logic_vector(RX_STREAMS*MVB_ITEMS*log2(RX_STREAMS)-1 downto 0)
in
RX SEL MVB: defines from which interface a word should be taken
RX_SEL_VLD
std_logic_vector(RX_STREAMS*MVB_ITEMS-1 downto 0)
in
RX SEL MVB: valid of each MVB item
RX_SEL_SRC_RDY
std_logic
in
RX SEL MVB: source ready
RX_SEL_DST_RDY
std_logic
out
RX SEL MVB: destination ready
TX_DATA
std_logic_vector(RX_STREAMS*MVB_ITEMS*MVB_ITEM_WIDTH-1 downto 0)
out
TX MVB: data word with MVB items
TX_VLD
std_logic_vector(RX_STREAMS*MVB_ITEMS-1 downto 0)
out
TX MVB: valid of each MVB item
TX_SRC_RDY
std_logic
out
TX MVB: source ready
TX_DST_RDY
std_logic
in
TX MVB: destination ready