MVB DEMUX

Multi-value bus item demultiplexer. For each item, there is a select signal, which determines to which TX port the item will be transmitted.

Transaction on RX MVB is executed, when all ports, to which at least one item will be transmitted, have DST_RDY asserted. Ports, which will not receive any item, do not have to have DST_RDY asserted.

ENTITY GEN_MVB_DEMUX IS

Multi-value bus item demultiplexer. For each item, there is a select signal, which determines to which TX port the item will be transmitted. Transaction on RX MVB is executed, when all ports, to which at least one item will be transmitted, have DST_RDY asserted. Ports, which will not receive any item, do not have to have DST_RDY asserted.

Generics

Generic

Type

Default

Description

MVB_ITEMS

natural

1

Any positive value

DATA_WIDTH

natural

64

Any positive value

DEMUX_WIDTH

natural

2

TX interfaces count

VERSION

string

“register”

OUTPUT_REG

boolean

False

INPUT_REG

boolean

false

Input register. This component will break, when connected to output of MVB_MERGE, since it can RX_VLD signal before transmission. In that case, enable this input register.

Ports

Port

Type

Mode

Description

CLK

std_logic

in

Clock signal

RESET

std_logic

in

Synchronous reset with CLK

=====

RX MVB interface

=====

Receive MVB interface with items to demultiplex.

RX_DATA

std_logic_vector(MVB_ITEMS * DATA_WIDTH - 1 downto 0)

in

This signal contains items, which will be demultiplexed

RX_SEL

std_logic_vector(MVB_ITEMS * max(1, log2(DEMUX_WIDTH)) - 1 downto 0)

in

This signal contains select signal for each item.

RX_VLD

std_logic_vector(MVB_ITEMS - 1 downto 0)

in

RX_SRC_RDY

std_logic

in

RX_DST_RDY

std_logic

out

=====

TX MVB interfaces

=====

DEMUX_WIDTH (amount) of transmit interfaces.

TX_DATA

std_logic_vector(DEMUX_WIDTH * MVB_ITEMS * DATA_WIDTH - 1 downto 0)

out

This signal contains demultiplexed items.

TX_VLD

std_logic_vector(DEMUX_WIDTH * MVB_ITEMS - 1 downto 0)

out

TX_SRC_RDY

std_logic_vector(DEMUX_WIDTH - 1 downto 0)

out

TX_DST_RDY

std_logic_vector(DEMUX_WIDTH - 1 downto 0)

in