Multi-port BRAM

ENTITY MP_BRAM IS

Multi-port BRAM. Currently supports only one write port. This will change in future. Amount of read ports is not restricted.

Generics

Generic	Type	Default	Description
DATA_WIDTH	integer	1	Data word width in bits. If BLOCK_ENABLE is True then DATA_WIDTH must be N*BLOCK_WIDTH.
BLOCK_WIDTH	integer	8	[1, inf] -> block width
BLOCK_ENABLE	boolean	False
ITEMS	integer	4096	Depth of BRAM in number of the data words.
OUTPUT_REG	boolean	True	Output directly from BRAM or throw register (better timing).
WRITE_PORTS	natural	1	Amount of write ports, currently supports just 1 write port.
READ_PORTS	natural	2	Amount of read ports. For each read port, BRAM is replicated to provide one read port.
METADATA_WIDTH	natural	0	metadata is data which is send with read request
UNDEF_BEHAW_WHEN_WR_TO_SAME_ADDRESS	boolean	True	when this generic is disabled then two port can write to same address in one clock cycle. Result are going to be undefined. This mean user have to secure there is no write to same address in same clock. Port wit lower id is prioritised and write data. If this generic is true then this architecture desnt support write to same address in same clock cycle from two ports
ONE_CLK_WRITE	boolean	False	If This generic is set to true then Write delay is shorter by bypassing Normal write delay is two clock cycles. If this generic is set to true tehn write delay is one clock.
DEVICE	string	“AGILEX”	The DEVICE parameter allows the correct selection of the RAM implementation according to the FPGA used. Supported values are: “7SERIES” “ULTRASCALE” “STRATIX10” “ARRIA10” “AGILEX”

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
=====	WRITE PORTS	=====	=====
WR_EN	std_logic_vector(WRITE_PORTS - 1 downto 0)	in	Enable of write port.
WR_ADDR	slv_array_t(WRITE_PORTS - 1 downto 0)(log2(ITEMS)-1 downto 0)	in	Write address.
WR_DATA	slv_array_t(WRITE_PORTS - 1 downto 0)(DATA_WIDTH-1 downto 0)	in	Write data input.
WR_BE	slv_array_t(WRITE_PORTS - 1 downto 0)(DATA_WIDTH/tsel(BLOCK_ENABLE, BLOCK_WIDTH, DATA_WIDTH+1)-1 downto 0)	in	ENABLE block. you can write only part of data into memory (“0011”) => write only down 16 bits Use work around when BOCK_WIDTH is zero then width of signal is NULL. (DATA_WIDTH/(DATA_WIDTH +1) == 0)
=====	READ PORTS	=====	=====
RD_EN	std_logic_vector(READ_PORTS - 1 downto 0)	in	Read enable signal, it is only used to generate RD_DATA_VLD.
RD_ADDR	slv_array_t(READ_PORTS - 1 downto 0)(log2(ITEMS)-1 downto 0)	in
RD_META_IN	slv_array_t(READ_PORTS - 1 downto 0)(METADATA_WIDTH-1 downto 0)	in
RD_DATA_VLD	std_logic_vector(READ_PORTS - 1 downto 0)	out	Read data output.
RD_DATA	slv_array_t(READ_PORTS - 1 downto 0)(DATA_WIDTH-1 downto 0)	out
RD_META_OUT	slv_array_t(READ_PORTS - 1 downto 0)(METADATA_WIDTH-1 downto 0)	out