Live value table memory
- ENTITY LVT_MEM IS
Multiported memory implementation inspired by https://dl.acm.org/doi/abs/10.1145/2629629 This approach is suitable for shallow memories since it implements smaller true multiported memories using registers. Thus underlying memories are implemented using LUTs (distmem for Xilinx). Also this memory supports read-during write NEW_DATA behaviour. Writes to same address from multiple ports in the same clock cycle result in undefined behaviour.
Generics
PortsGeneric
Type
Default
Description
DATA_WIDTH
natural
16
Stored data width
ITEMS
natural
64
Depth of memory
READ_PORTS
natural
2
Amount of read ports
WRITE_PORTS
natural
2
Amount of write ports
RD_LATENCY
natural
1
Read latency - 0 or 1
RDW_BEHAV
string
“NEW_DATA”
Read during write behaviour: “NEW_DATA” or “DONT_CARE”.
MEM_TYPE
string
“BRAM”
Underlying memory type: “BRAM” or “LUT”. When using BRAM, RD_LATENCY must be set to 1.
DEVICE
string
“AGILEX”
Port
Type
Mode
Description
CLK
std_logic
in
RESET
std_logic
in
WR_EN
std_logic_vector(WRITE_PORTS-1 downto 0)
in
WR_ADDR
slv_array_t(WRITE_PORTS-1 downto 0)(log2(ITEMS)-1 downto 0)
in
WR_DATA
slv_array_t(WRITE_PORTS-1 downto 0)(DATA_WIDTH-1 downto 0)
in
RD_ADDR
slv_array_t(READ_PORTS-1 downto 0)(log2(ITEMS)-1 downto 0)
in
RD_DATA
slv_array_t(READ_PORTS-1 downto 0)(DATA_WIDTH-1 downto 0)
out