Multi-port BRAM

ENTITY MP_BRAM IS

Multi-port BRAM. Currently supports only one write port. This will change in future. Amount of read ports is not restricted.

Generics

Generic	Type	Default	Description
DATA_WIDTH	integer	1	Data word width in bits. If BLOCK_ENABLE is True then DATA_WIDTH must be N*BLOCK_WIDTH.
ITEMS	integer	4096	Depth of BRAM in number of the data words.
BLOCK_ENABLE	boolean	False	Enable masking of WR_DATA signal per BLOCK_WIDTH.
BLOCK_WIDTH	natural	8	Width of one data block. Allowed values are 8 or 9. The parameter is ignored when BLOCK_ENABLE=False.
OUTPUT_REG	boolean	True	Output directly from BRAM or throw register (better timing).
METADATA_WIDTH	integer	0	Width of read metadata signal
WRITE_PORTS	natural	1	Amount of write ports, currently supports just 1 write port.
READ_PORTS	natural	2	Amount of read ports. For each read port, BRAM is replicated to provide one read port.
DEVICE	string	“AGILEX”	The DEVICE parameter allows the correct selection of the RAM implementation according to the FPGA used. Supported values are: “7SERIES” “ULTRASCALE” “STRATIX10” “ARRIA10” “AGILEX”

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RESET	std_logic	in
=====	WRITE PORTS	=====	=====
WR_EN	std_logic_vector(WRITE_PORTS - 1 downto 0)	in	Enable of write port.
WR_BE	slv_array_t(WRITE_PORTS - 1 downto 0)(max((DATA_WIDTH/BLOCK_WIDTH),1)-1 downto 0)	in	Block enable of written data, used only when BLOCK_ENABLE = True.
WR_ADDR	slv_array_t(WRITE_PORTS - 1 downto 0)(log2(ITEMS)-1 downto 0)	in	Write address.
WR_DATA	slv_array_t(WRITE_PORTS - 1 downto 0)(DATA_WIDTH-1 downto 0)	in	Write data input.
=====	READ PORTS	=====	=====
RD_EN	std_logic_vector(READ_PORTS - 1 downto 0)	in	Read enable signal, it is only used to generate RD_DATA_VLD.
RD_PIPE_EN	std_logic_vector(READ_PORTS - 1 downto 0)	in	Clock enable of read port.
RD_META_IN	slv_array_t(READ_PORTS - 1 downto 0)(METADATA_WIDTH-1 downto 0)	in	Metadata propagated when RD_PIPE_EN==’1’ (valid on RD_EN)
RD_ADDR	slv_array_t(READ_PORTS - 1 downto 0)(log2(ITEMS)-1 downto 0)	in	Read address.
RD_DATA	slv_array_t(READ_PORTS - 1 downto 0)(DATA_WIDTH-1 downto 0)	out	Read data output.
RD_META_OUT	slv_array_t(READ_PORTS - 1 downto 0)(METADATA_WIDTH-1 downto 0)	out	Metadata propagated when RD_PIPE_EN==’1’ (valid on RD_DATA_VLD)
RD_DATA_VLD	std_logic_vector(READ_PORTS - 1 downto 0)	out	Valid bit of output read data.