Synchronous SR latch

ENTITY SR_SYNC_LATCH IS

This component provides synchrnous SR latch behavior with some enhancements:

1. The forbidden state when both SET and RESET are asserted has been removed. In this case, the design behaves in the same way when both signals are deasserted, e.g. it keeps its output unchanged.

2. Data being latched could be set to arbitrary length so whole bus data can be latched to the output.

3. The design is driven by clock signal so it is not purely combinatorial circuit. This is the advantage when meeting time closure.

Generics

Generic	Type	Default	Description
DATA_WIDTH	positive	32	Width of the data being latched.

Ports

Port	Type	Mode	Description
CLK	std_logic	in
SET	std_logic	in	When asserted, the data from DATA_IN are latched to the output LATCH_OUT
RESET	std_logic	in	When asserted, the data on the output LATCH_OUT are cleared.
DATA_IN	std_logic_vector((DATA_WIDTH - 1) downto 0)	in	Input data to being latched, usage of this port is optional.
LATCH_OUT	std_logic_vector((DATA_WIDTH - 1) downto 0)	out

Note

To set this component to behave as a one bit latch, simply omit to connect the DATA_IN input.