ASFIFOX

ENTITY ASFIFOX IS

A universal asynchronous (dual clock) FIFO, suitable both for Xilinx and Intel (Altera) FPGA. Can be parametrically implemented in BRAM or LUTRAM (MLAB on Intel FPGA = 32 items, distributed memory in Xilinx FPGA = 64 items).

Generics

Generic	Type	Default	Description
DATA_WIDTH	natural	512	Data word width in bits.
ITEMS	natural	512	FIFO depth in number of data words, must be a power of two! Minimum value is 2.
RAM_TYPE	string	“BRAM”	Select memory implementation. Options: “LUT” - effective for shallow FIFO (approx. ITEMS <= 64), “BRAM” - effective for deep FIFO (approx. ITEMS > 64).
FWFT_MODE	boolean	True	First Word Fall Through mode. If FWFT_MODE=True, valid data will be ready at the ASFIFOX output without RD_EN requests.
OUTPUT_REG	boolean	True	Enabled output registers allow better timing for a few flip-flops.
DEVICE	string	“ULTRASCALE”	The DEVICE parameter allows the correct selection of the RAM implementation according to the FPGA used. Supported values are: “7SERIES” “ULTRASCALE” “STRATIX10” “ARRIA10” “AGILEX”
ALMOST_FULL_OFFSET	natural	ITEMS/2	Determines how few data words must be left free for WR_AFULL to be triggered. (currently_stored >= ( ITEMS - ALMOST_FULL_OFFSET)
ALMOST_EMPTY_OFFSET	natural	ITEMS/2	Determines how few data words must be stored for RD_AEMPTY to be triggered. ( currently_stored <= ALMOST_EMPTY_OFFSET )

Ports

Port	Type	Mode	Description
=====	WRITE INTERFACE	=====	=====
WR_CLK	std_logic	in	Clock for write interface
WR_RST	std_logic	in	Reset for write interface. Does not affect reset on read side
WR_DATA	std_logic_vector(DATA_WIDTH-1 downto 0)	in	Data to be written; must be valid when WR_EN = '1'
WR_EN	std_logic	in	Indicates the validity of WR_DATA. Can be connected as SRC_RDY.
WR_FULL	std_logic	out	Writing is accepted only when WR_FULL=0, otherwise it is ignored. Can be connected as “not DST_RDY”.
WR_AFULL	std_logic	out	Set to '1' when less than ALMOST_FULL_OFFSET space is left for writing items.
WR_STATUS	std_logic_vector(log2(ITEMS) downto 0)	out	Indicates the number of items currently stored in the FIFO
=====	READ INTERFACE	=====	=====
RD_CLK	std_logic	in	Clock for read interface
RD_RST	std_logic	in	Reset for read interface. Does not affect reset on write side
RD_DATA	std_logic_vector(DATA_WIDTH-1 downto 0)	out	Data available for reading; valid when RD_EMPTY = '0'
RD_EN	std_logic	in	Set to '1' to request or accept valid data on RD_DATA. Can be connected as DST_RDY.
RD_EMPTY	std_logic	out	When in '0' indicates valid data on RD_DATA. Can be connected as “not SRC_RDY”.
RD_AEMPTY	std_logic	out	Set to '1' when less than ALMOST_EMPTY_OFFSET items are left for reading.
RD_STATUS	std_logic_vector(log2(ITEMS) downto 0)	out	Indicates the number of items currently stored in the FIFO. Items in output registers are also included in the calculation. There may be cases where RD_STATUS > 0 and data are not yet available at the output (RD_EMPTY = '1').

Block diagram