Pulse short

ENTITY PULSE_SHORT IS

This component allows to shorten arbitrary long pulse on the input TRIGGER to only one clock period short pulse (driven by the BCLK). Outuput pulse can be arbirarily delayed when DELAY_COUNT constant is set. Optional CDC could be applied on control inputs by setting specific bits in the ASYNC_MASK generic constant.

Generics

Generic	Type	Default	Description
DELAY_COUNT	natural	0	Controls for how much clock cycles should the output be delayed. Maximum value is 1 048 575 because I don’t think you need to delay one pulse even for that long
ASYNC_MASK	std_logic_vector(2 downto 0)	“000”	controls whether specific input should be connected throgh clock domain crossings: bit 0 -> RST, bit 1 -> EN, bit 2 -> TRIGGER

Ports

Port	Type	Mode	Description
ACLK	std_logic	in	Input clock, usage is optional but needs to be used when some bit in the ASYNC_MASK generic parameter is set to 1
BCLK	std_logic	in	Output clock
RST	std_logic	in	Reset signal
EN	std_logic	in	Enable signal, usage is optional
TRIGGER	std_logic	in	Input triggering pulse
PULSE_OUT	std_logic	out	Output pulse with one BCLK period duration