Frequency meter
- ENTITY FREQUENCY_METER IS
The component FREQUENCY_METER measures frequency of a (Clock) signal using the Equal Precision algorithm. For this, it needs a reference (Clock) signal of known frequency.
The “Measured frequency” is measured within an Interval, which is configurable via the MI bus (see the MI Address Space below). Start the measurement by a Write to the Command register. During this Interval, two counters are enabled, one running on the Reference Clock, the other on the Measured Clock. After it has passed, the counters’ data will be ready to be fetched (=> loaded to MI registers). Check the Status register for information about whether the measurement is running or has completed, if the data are ready, or if any errors occurred (and which one(s)).
Note
In the case of an overflow error (status(6-7)), either make a new design with wider counter(s) or just lower the duration of the measurement by writing a new value to the Interval length register. Be aware that lower lengths of the Interval (slightly) decrease the accuracy of the measurement.
Note
Issuing a MI reset command (cmd(1)) during an in-progress measurement without stopping it (re)starts the measurement anew, so there is no need to start it again by writing to the command register (cmd(0)).
The component cannot calculate the final frequency (is not yet implemented). At this time, it can simply be done in software using formula: Fmeas = Fref * Nmeas/Nref, where F<meas/ref> is the Measured or Reference frequency and N<meas/ref> are the data from the counters. It is recommended to use the provided python tool to calculate the final value of the measured frequency(ies).
Other yet-to-be-implemented features include storing the counters’ values from multiple measurements and a histogram of these values.
MI Address Space
Generics
PortsGeneric
Type
Default
Description
MI_DATA_WIDTH
natural
32
MI_ADDR_WIDTH
natural
32
INTERVAL_LEN_WIDTH
natural
32
Maximum width of the Interval length signal => the highest possible value is 2**INTERVAL_LEN_WIDTH-1. This value of the Interval length signal can be set over the MI. Defines the length of the Interval during which the frequency measurement takes place. Counts by 1 to its maximum which is when the “frequency counters” are sampled. Values over 32 (=MI_DATA_WIDTH) are currently not supported!
REFERENCE_CNTR_WIDTH
natural
31
Width of the “Reference Frequency Counter”. Watch out for overflow (indicated by a bit in the Status register). Must not be over 32!
MEASURED_CNTR_WIDTH
natural
31
Width of the “Measured Frequency Counter” (all of them if there is more than one). Watch out for overflow (indicated by a bit in the Status register). Must not be over 32!
MEASURED_FREQUENCIES
natural
10
Maximum number of measured frequencies.
REFERENCE_CLK_FREQ
natural
200_000_000
Frequency of the reference clock signal in Hz. Used in the final calculation when the CALCULATE_FREQ generic is True. Recommended to read before the SW calculation (when the CALCULATE_FREQ generic is False).
DSP_CNTR_EN
boolean
False
Utilize DSPs for both “frequency counters”.
CALCULATE_FREQ
boolean
False
Calculate the unknown frequency in the FPGA. Uses extra resources. Not supported yet!
STORE_DATA_EN
boolean
False
Store measured data and/or calculated frequencies in a FIFO to read out later. Could be useful for further analysis. Not supported yet! (Also leads to a generic for FIFO_SIZE)
HISTOGRAM_EN
boolean
False
Store measured data and/or calculated frequencies in a histogram. Could be useful for further analysis. Not supported yet!
DEVICE
string
“AGILEX”
Target device.
Port
Type
Mode
Description
REFERENCE_CLK
std_logic
in
REFERENCE_RESET
std_logic
in
MEASURED_CLK
std_logic_vector(MEASURED_FREQUENCIES-1 downto 0)
in
MEASURED_RESET
std_logic_vector(MEASURED_FREQUENCIES-1 downto 0)
in
MI_CLK
std_logic
in
MI interface
MI_RESET
std_logic
in
MI_DWR
std_logic_vector(MI_DATA_WIDTH-1 downto 0)
in
MI_ADDR
std_logic_vector(MI_ADDR_WIDTH-1 downto 0)
in
MI_RD
std_logic
in
MI_WR
std_logic
in
MI_ARDY
std_logic
out
MI_DRD
std_logic_vector(MI_DATA_WIDTH-1 downto 0)
out
MI_DRDY
std_logic
out