Memory Logger

The Mem Logger is a wrapper around the DATA_LOGGER component. It logs simple statistics about a memory interface.

Usage example can be found in the MEM_TESTER component.

Key Features

Measured Statistics

Number of read and write requests
Number of transferred words (separately tracks requested read words vs. actually received read words)
Number of clock cycles between first and last transaction for:
- Read operations
- Write operations
- Combined read + write traffic
(software can calculate effective data throughput from these)
Read request latencies:
- Minimum, maximum and average latency
- Latency histogram
Internally uses the LATENCY_METER and HISTOGRAMER components.

Configuration

Option to measure read latency to the first or last received word (default: last word)

Component port and generics description

ENTITY MEM_LOGGER IS

Generics

Generic	Type	Default	Description
MEM_DATA_WIDTH	integer	512
MEM_ADDR_WIDTH	integer	26
MEM_BURST_COUNT_WIDTH	integer	7
MEM_FREQ_KHZ	integer	300000
MI_DATA_WIDTH	integer	32
MI_ADDR_WIDTH	integer	32
HISTOGRAM_BOXES	integer	256	Specify read latency histogram precision
MAX_PARALEL_READS	integer	128	Specify maximum paraller read requests
LATENCY_TICKS_WIDTH	integer	12	Specify read latency ticks count width
MEM_ASYNC	boolean	true
DEVICE	string	“AGILEX”

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RST	std_logic	in	Synchronous to CLK
RST_DONE	std_logic	out	Synchronous to CLK
=====	Memory interface	=====	=====
MEM_CLK	std_logic	in
MEM_RST	std_logic	in
MEM_READY	std_logic	in
MEM_READ	std_logic	in
MEM_WRITE	std_logic	in
MEM_ADDRESS	std_logic_vector(MEM_ADDR_WIDTH - 1 downto 0)	in
MEM_READ_DATA	std_logic_vector(MEM_DATA_WIDTH - 1 downto 0)	in
MEM_WRITE_DATA	std_logic_vector(MEM_DATA_WIDTH - 1 downto 0)	in
MEM_BURST_COUNT	std_logic_vector(MEM_BURST_COUNT_WIDTH - 1 downto 0)	in
MEM_READ_DATA_VALID	std_logic	in
=====	MI bus interface	=====	=====
MI_DWR	std_logic_vector(MI_DATA_WIDTH - 1 downto 0)	in
MI_ADDR	std_logic_vector(MI_ADDR_WIDTH - 1 downto 0)	in
MI_BE	std_logic_vector(MI_DATA_WIDTH / 8 - 1 downto 0)	in
MI_RD	std_logic	in
MI_WR	std_logic	in
MI_ARDY	std_logic	out
MI_DRD	std_logic_vector(MI_DATA_WIDTH - 1 downto 0)	out
MI_DRDY	std_logic	out

Instance template (simple usage)

mem_logger_i : entity work.MEM_LOGGER
generic map (
    MEM_DATA_WIDTH          => MEM_DATA_WIDTH       ,
    MEM_ADDR_WIDTH          => MEM_ADDR_WIDTH       ,
    MEM_BURST_COUNT_WIDTH   => MEM_BURST_WIDTH      ,
    MEM_FREQ_KHZ            => AMM_FREQ_KHZ         ,

    MI_DATA_WIDTH           => MI_DATA_WIDTH        ,
    MI_ADDR_WIDTH           => MI_ADDR_WIDTH
)
port map (
    CLK                     => MEM_CLK                  (i),
    RST                     => MEM_RST                  (i),

    MEM_READY               => MEM_AVMM_READY           (i),
    MEM_READ                => MEM_AVMM_READ            (i),
    MEM_WRITE               => MEM_AVMM_WRITE           (i),
    MEM_ADDRESS             => MEM_AVMM_ADDRESS         (i),
    MEM_READ_DATA           => MEM_AVMM_READDATA        (i),
    MEM_WRITE_DATA          => MEM_AVMM_WRITEDATA       (i),
    MEM_BURST_COUNT         => MEM_AVMM_BURSTCOUNT      (i),
    MEM_READ_DATA_VALID     => MEM_AVMM_READDATAVALID   (i),

    MI_DWR                  => mem_mi_dwr               (i),
    MI_ADDR                 => mem_mi_addr              (i),
    MI_BE                   => mem_mi_be                (i),
    MI_RD                   => mem_mi_rd                (i),
    MI_WR                   => mem_mi_wr                (i),
    MI_ARDY                 => mem_mi_ardy              (i),
    MI_DRD                  => mem_mi_drd               (i),
    MI_DRDY                 => mem_mi_drdy              (i)
);

Control Software

For installation instructions, see the DATA_LOGGER documentation.

You can use the mem_logger Python module from your own scripts, or run the tool directly:

python3 mem_logger.py