TSU GEN

ENTITY TSU_GEN IS

The TimeStamp Unit is used to generate accurate 64b timestamps in two different formats (see the description of the TS and TS_NS ports). Conversion to another format, where the whole Timestamp represented as a number of nanoseconds, is available with the TSU_FORMAT_TO_NS component (one directory above).

The TSU supports a pulse per second (PPS) external signal, for example, from a precision GPS receiver. The TSU must be properly configured and activated to start. Configuration is performed by the software tool via the MI interface.

MI address space:

Registers accessible directly via the MI bus:
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0x00 = MI_DATA_REG, low part (32b, RW)
0x04 = MI_DATA_REG, middle part (32b, RW)
0x08 = MI_DATA_REG, high part (32b RW)
0x0C = Control register (CTRL_REG) (3b, WO):
     - "000" write MI_DATA_REG  to INCR_VAL_REG;
     - "001" write MI_DATA_REG  to REALTIME_REG;
     - "100" write INCR_VAL_REG to MI_DATA_REG;
     - "101" write REALTIME_REG to MI_DATA_REG;
     - "111" write PPS_REG      to MI_DATA_REG;
0x10 = State register detection of clk and pps activity (2b, RO):
     - bit 0: PPS activity detection
     - bit 1: clock activity detection
0x14 = INTA register (1b, WO):
     - Valid bit register sets the value of the TS_DV output signal.
0x18 = Select PPS source (1-32b, RW):
     - PPS source with higher number should be more precise.
0x1C = Actual TSU clock frequency (32b, RO):
     - Frequency format: 0=1Hz, 1=2Hz, 2=3Hz...
0x20 = TSU clock source multiplexor address (1-32b, RW):
     - CLK source with higher number should be more precise.
0x24 = Number of available CLK and PPS sources (32b, RO):
     - Lower half (16b) contains the number of available PPS sources.
     - Higher half (16b) contains the number of available clock sources.

Registers accessible through CTRL_REG and MI_DATA_REG only:
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- INCR_VAL_REG = Incremental value register (39b, RW)
- REALTIME_REG = Real-time register (96b, RW)
- PPS_REG = Register PPS (96b, RO)

Generics

Generic	Type	Default	Description
TS_MULT_SMART_DSP	boolean	true	Selects smarter DSPs arrangement for timestamp format conversion. Meanings of supported values: true = use multiplication in DSPs composed of adds and shifts; false = look at TS_MULT_USE_DSP
TS_MULT_USE_DSP	boolean	true	Selects whether to use DSPs for timestamp format conversion: Meanings of supported values: true = use multipliers in DSPs; false = disable DSPs, use logic
PPS_SEL_WIDTH	integer	8	Width of PPS select signal: Used value must be in range from 1 to 16. Should be greater or equal to base 2 logarithm from number of available PPS sources.
CLK_SEL_WIDTH	integer	8	Width of main CLK select signal: Used value must be in range from 1 to 16. Should be greater or equal to base 2 logarithm from number of available CLK sources.
DEVICE	string	“ULTRASCALE”	Name of selected FPGA device

Ports

Port	Type	Mode	Description
=====	Signals for MI32 interface	=====	=====
MI_CLK	std_logic	in	Clock for MI32 interface.
MI_RESET	std_logic	in	Synchronious reset with MI_CLK.
MI_DWR	std_logic_vector(31 downto 0)	in	MI bus: data from master to slave (write data)
MI_ADDR	std_logic_vector(31 downto 0)	in	MI bus: slave address
MI_RD	std_logic	in	MI bus: read request
MI_WR	std_logic	in	MI bus: write request
MI_BE	std_logic_vector(3 downto 0)	in	MI bus: byte enable, not supported in this component!
MI_DRD	std_logic_vector(31 downto 0)	out	MI bus: data from slave to master (read data)
MI_ARDY	std_logic	out	MI bus: ready of slave module
MI_DRDY	std_logic	out	MI bus: valid of MI_DRD data signal
=====	PPS signal interface	=====	=====
PPS_N	std_logic	in	Input PPS_N signal
PPS_SRC	std_logic_vector(15 downto 0)	in	Number of different PPS sources (on MI_CLK)
PPS_SEL	std_logic_vector(max(PPS_SEL_WIDTH-1,0) downto 0)	out	Select PPS source (on main CLK)
=====	Main CLK signal interface	=====	=====
CLK	std_logic	in	Input CLK signal (main clock)
RESET	std_logic	in	Synchronious reset with main clock
=====	CLK signal configuration interface	=====	=====
CLK_FREQ	std_logic_vector(31 downto 0)	in	Frequency of input CLK signal (on MI_CLK)
CLK_SRC	std_logic_vector(15 downto 0)	in	Number of different CLK sources (on MI_CLK)
CLK_SEL	std_logic_vector(max(CLK_SEL_WIDTH-1,0) downto 0)	out	Select CLK source (on MI_CLK)
=====	Output timestamp interface (on main CLK)	=====	=====
TS	std_logic_vector(63 downto 0)	out	Timestamp in fractional (old) format: Fractional part of timestamp represents number of xanoseconds (one xanosecond is 2^(-32) seconds).
TS_NS	std_logic_vector(63 downto 0)	out	Timestamp in nanosecond (new) format: Fractional part of timestamp represents number of nanoseconds (one nanosecond is 10^(-9) seconds). Maximum number of nanoseconds is 999 999 999, therefor highest 2 bits of fractional part are unused.
TS_DV	std_logic	out	Timestamp is valid in this cycle